BSc IT Sem I 2017 18 2017-18 Digital Electronics Question Paper - Mumbai University | munotes

Questions asked in this paper

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1. Q2 Make suitable assumptions wherever necessary and state the assumptions made
2. Q3 Answer to the same question must be written together
3. Q4 Numbers to the right indicate marks
4. Q6 Use of Non-programmable calculators is allowed
5. Q1 Attemptany three of the following: 15 marks
   • a. Write the difference between analog signal and digital signal
   • b. Convert the following numbers
   • c. Convert the given
   • d. Find
   • i) The Gray code equivalent of Decimal 13
   • ii) Binary equivalent of Gray code 1111
   • iii) Hexadecimal equivalent of octal (765)
   • iv) Octal equivalent of binary(1100111110101)
   • v) Decimal equivalent of binary 1010101010
   • e. Write note on Error correction and detection code
   • f. i) Perform the addition of following Binary number
   • ii) Perform the Subtraction of following Binary numbers using 1’s complement method
6. Q2 Attemptany three of the following: 15 marks
   • a. logic expression Y=AB+A’B' Obtain the truth table, name the operation performed, realize the operation using AND, OR, NOT gate Also realize it using NAND gate only
   • b. Draw the output wave form of AND gate and explain it’s operation. Also, discuss about 4 input
   • c. Prove the following using Boolean law
   • d. Reduce the given SOP equation using K-map method and draw the circuit using NAND network Reduce the given POS function using K-map and draw the circuit diagram using NOR network Using Don’t care condition find reduced SOP equation and draw the circuit diagram using basic
   • Q.P. Code :00906
7. Q3 Attemptany three of the following: 15 marks
   • a. Design the Half adder using K-map. Draw the circuit diagram for the same
   • b. With the help of circuit diagram discuss four bit binary adder-subtractor
   • d. Write a short note on BCD to EXCESS-3 code converter
   • e. Multiplier? Draw diagram and explain 4x4 bit multiplier
   • f. Explain Full Adder in detail
8. Q4 Attemptany three of the following: 15 marks
   • a. Draw the logic diagram of 4 to 1 multipexer. Explain its working
   • b. Write a short note on demultipexer
   • c. Define cascading. Design 16 to 1 multipexer using 8 to 1 multipexer
   • d. With the help of diagram explain Bistable Multivibrator
   • e. What is meant by race around problem? Explain master slave flip-flop
   • f. How J-K flip-flop can used to form aD flip-flop
9. Q5 Attemptany three of the following: 15 marks
   • a. Write note on modulus of counter
   • b. Explain the working of four bit UP/DOWN counter
   • c. Determine the number of flip-flops in Mod 10 ring counter and Jonson counter. Write count sequence in both the cases
   • d. Briefly describe the architecture of SISO shift register
   • e. Explain the design procedure for MOD 8 binary counter
   • f. The table gives below the excitation of flip-flop having inputs X1 and X2. Draw the circuit excitation table of Mod -5 synchronous this flip-flop for the counter sequence 000,001,010,011,100,000. Design the counter using flip-flop whose excitation table is given below

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