Engineering BE Electronics and Computer Science Sem 5 December 2018 2018 ASIC VerificationDLOCElective I Question Paper - Mumbai University | munotes

Questions asked in this paper

1. Q1 Solve the following (Any four) 20 marks
   • A. What is the significance of ‘scope resolution operator’
   • B. Justify if code coverage is 100%, it indicates verification is done 100%
   • C. Short note on mailbox and describe their use in System Verilog with suitable example
   • D. Explain the concept of an interface with suitable example and why it is used?
   • E. Draw layered test bench block diagram.mentioning each layer clearly
2. Q2 A. Draw the architecture of FPGA and specify its important components. Highlight the features of Virtex — 7. [10]
   • B. Explain the concept of Switch level modelling. Write Verilog code for 2:1 mux using
3. Q3 A. Discuss Silicon challenges considering time closure, capacity, physical properties, design productivity gap and time to market. [10]
   • i. Create an unpacked array, ‘my_array’, containing 4 elements of user defined
   • ii. Initialize it to 4’hA, and 4’hD
   • iii. Stream my_array into my_array_s, right to left on a bit basis and print out the following code, determine what will be displayed
4. Q4 A. For the following interface, add the system verilog code: interface my_if (input bit clk); bit [15:0] data_in; 10 marks
   • i) A clocking block that is sensitive to negative of the clock and that are synchronous to the clock
   • ii) A modport for Testbench called Master A modport for DUT called Slave
   • B. Explain immediate and concurrent assertions in detail. 10
5. Q5 A. Explain how communication between threads is achieved with fork.join, fork.join_none and any: Give example 10 marks
   • B. What is cross coverage, code coverage and function coverage? Explain with proper
6. Q6 A. Explain System Verilog Constraint Random stimulus generation with suitable example
   • B. Write a covergroup to collect coverage on the test plan requirement with 10
7. Q1 The opcode shall take on the values ADD or SUB (Use 1
8. Q2 The opcode shall take on the values ADD followed by SUB
9. Q3 Opcode must not equal DIV” (hint: report an error using illegal_bins)

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