Engineering BE Electrical Engineering Sem 4 May 2023 2023 ELEC4Control System Design Question Paper - Mumbai University | munotes

Questions asked in this paper

1. Q1 1 is compulsory
2. Q2 Answer any three questions from Q. No.2 toQ. No. 6 marks
3. Q3 Write in legible handwriting
4. Q4 Make any suitable assumptions wherever required
5. Q5 Must make suitable supporting diagrams wherever desired
6. Q6 Figure to the right indicates marks question carries five marks 20
   • a. Why is the phase margin increased above that desired when designing a
   • b. Define observability. Explain how it can be determined for a controller
   • c. Why is there less improvement in steady-state error if a lag controller is used instead of a PI controller?
   • d. The horizontal lines on the s-plane are lines of constant peak time. How these points can be mapped to z-plane? Justify with the equation Q Given the unity feedback system with G(s)= Root locus technique to determine the value of gain K to yield a step response
   • b. ay 10 10 Given the following open loop plant G(s) Design a controller to yield al5% overshoot and a peak time of 0.4 sec assuming that the plant is represented in the phase variables form. Assume third pole 10 times farther from the imaginary axis than the dominant poles
7. Q3 a. For digital system with forward transfer function G(z)= find the static error constants and the steady state error if the inputs are u(t), t u(t) and —u(t). Sampling time T=0.1 For a unity feedback system with G(s)= design a lag compensator using bode plot so that the system operates with a 10% overshoot and a static error constant of 100 Q Consider the plant G(s) = which is represented in parallel form. Design an observer with a transient response described by C=0.45 and wn=100. Place the observer third pole 10 times as far from the imaginary axis as the observer dominant poles. Transform the plant to observer canonical form for the design. Then transform the design back to parallel form 10 marks
   • b. Find G(z) for G(s)= in cascade with a sampler and a zero-order sample 05 and hold. The sampling period is 0.25
8. Q5 a. A unity feedback system with forward path transfer function G(s)= has 15% overshoot. Evaluate the current dominant poles using R.L and then design a PD controller to reduce the settling time by a factor of 2 10 marks
   • b. Given a sampler and z.o.h. in cascade with G(s)= find the range of 10 T to make the system stable
9. Q6 a. Given the plant Design an integral controller to yield a 12% overshoot, 2 sec. settling time and zero steady state error for a step input 10 marks
   • b. Compare lag and lead compensator with respect to application, pole- 10 zero plot and circuit for implementation. Construct the transfer functions of lag and lead compensators from their respective circuits

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