Engineering BE Computer Engineering Sem 3 May 2024 2024 Digital Logic & Computer Architecture Question Paper - Mumbai University | munotes

Questions asked in this paper

1. Q1 Question Number | is compulsory
2. Q2 Solve any three questions out of remaining five questions
3. Q3 Each Question carry 20 marks
4. Q4 Illustrate your answers with neat sketches wherever necessary
5. Q5 Figures to the right indicate full marks
6. Q6 Assume suitable additional data, if necessary and clearly state it
7. Q7 All sub-questions of the same question should be grouped together
8. Q1 (a) 1.) Simplify the Boolean expression: A AND (B OR (C AND D)) using li.) Create a truth table for the following circuit: A AND (B OR C). 02 3 marks
   • (b) Convert the IEEE-754 single-precision representation 05 0 10000010 to its decimal equivalent
   • (c) Discuss the significance of Decoders in address decoding. Provide the truth 05 table for a 3-to-8 Decoder
   • (d) Draw and explain Microinstruction sequencing organization. 05
9. Q2 (a) A block-set associative cache memory consists of 128 blocks divided into four block sets. The main memory consists of 16,384 blocks and each block 10 marks
   • i.) How many bits are required for addressing the main memory?
   • ii.) How many bits are needed to represent the TAG, SET and WORD
   • (b) What is bus arbitration? Explain any two techniques of bus arbitration? 10
10. Q3 (a) Draw and explain the operation of a Master-Slave J-K Flip-Flop with PRESET and CLEAR. How does it differ from a regular J-K flip-flop? 10 marks
    • (b) Explain the concept of a microprogrammed control unit and compare it with 10 a hardwired control unit. Describe the advantages and disadvantages of using
11. Q4 (a) Explain how the NAND gate can be used as a universal logic gate. Provide examples of how it can be used to implement other logic gates 10 marks
    • (b) How Booth's multiplication algorithm can be used to multiply and 10 binary numbers. Show the intermediate steps involved multiplication process and explain how the final result is obtained
12. Q5 (a) Perform the following binary arithmetic operations and show the intermediate steps and the final result 10 marks
    • i.) Add the following Binary Coded Decimal (BCD) numbers:
    • ii.) Subtract the following binary numbers using 2's complement
    • ii.) Multiply the following binary numbers using 1's complement
    • iv.) Divide the following binary numbers using 2's complement
    • v.) Perform addition in hexadecimal for the numbers: (2A) + (1B)
    • (b) What is Pipeline Hazard? Give the types of pipeline hazards. Write a 10 difference between delayed branch and branch prediction
13. Q6 (a) Draw instruction cycle state diagram with interrupt. 5 marks
    • (b) is State Table Method used for design Hardwired Control unit? 05
    • (c) Compare with suitable parameters SRAM with DRAM. 05
    • (d) Draw the neat block diagram for Flynn's classification. 05

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