Engineering BE Computer Engineering Sem 3 December 2022 2022 Digital Logic And Computer Architecture Question Paper - Mumbai University | munotes

Questions asked in this paper

1. Q2 Attempt any three questions from remaining five questions
2. Q3 Assume suitable data if necessary and justify the assumptions
3. Q4 Figures to the right indicate full marks
4. Q1 123 in to binary
   • ii) in to Decimal (351)s in to decimal
   • iv) 129 in to BCD
   • v) 64 in to gray code B_ Draw the single and double precision format for representing floating point number 05 using IEEE 754 standards and explain the various fields C Explain SR Flip Flop 05 Differentiate between Hardwired control unit and Micro programmed control unit 05
5. Q2 Draw the flow chart of Booths algorithm for signed multiplication and Perform - Explain the different addressing modes. 10 10 marks
6. Q3 For 132.65 obtain the IEEE 754 standards of Single precision and Double precision Explain Micro instruction format and write a microprogram for the instruction 10 10 marks
7. Q4 A_ Consider a 4-way set associative mapped cache with block size 4 KB. The size of the main memory is 16 GB and there are 10 bits in the tag. Find 10 marks
8. Q1 Size of cache memory Explain Flynn’s classification 10
9. Q5 different types Distributed and Centralized bus arbitration methods Describe the detailed Von-Neumann Model with a neat block diagram 05 C_ Describe the characteristics of Memory. 05 10 marks
10. Q6 Write Short notes on 20 marks
    • a) Grey code, BCD, Excess-3 Code with example
    • c) Cache coherence
    • d) Instruction Pipelining

Read from the scan above, so a character or two may differ. The scan is the original.