BSc Sem III 2023 2024 2024 PHYSICS II Question Paper - Mumbai University | munotes

Questions asked in this paper

• 2) Figures to the right indicate maximum marks

1. Q1 A) Attempt any one question. [10 M}
   • i) Describe how fixed bias is achieved for CE amplifiers .State its advantages and disadvantages
   • ii) What is faithful amplification? State and explain the condition to be fulfilled to achieve faithful amplification in a transistorized amplifier
2. Q1 B) Attempt any two question. [10 M]
   • i) It is desired to set the Operating point at 4V, 1.2mA by biasing the silicon transistor with collector feedback resistor Rp. If B=120, find the value of Rp = ii) Explain the following terms a) Current gain (b) Voltage gain
   • iii) The input signal voltage of an amplifier is 2V and the input ascent is Ims. The output current is 20 mA through a load resistor of 6000Q .Determine input resistance of the amplifier
   • iv) In collector feedback biased silicon transistor circuit, =1K B=100.Determine the operating point if Vec= +10V
3. Q2 A) Attempt any one question. [10 M]
   • i) Explain the concept of differentiator with a neat labeled circuit diagram and obtain the expression of output voltage for the same
   • ii) Draw neat labeled diagrams for the summing amplifier and obtain an expression for output voltage and state applications of the summing amplifier
4. Q2 B) Attempt any two questions. [10 M]
   • i) To have a gain of 25 for an inverting Op-Amp, what should be the feedback resistor required? Given input resistance is 400 Q
   • ii) Write a short note on the critical frequency of the integrator ili) Explain the concept of frequency response of Op-Amp
   • iv) What will be the maximum frequency that can be applied without distortion if the gain bandwidth product of Op-Amp is | MHz Given: For negative feedback gain is 100
5. Q3 A) Attempt any One question. [10 M]
   • i) What is the shortcoming of R-S flip-flop? Explain how it is removed in JK flip-flops. Describe how the J-K flip-flop is realized .Describe its operation
   • ii) Draw a block diagram of an up-down ripple counter .Explain its Operation. Give its truth table for the countdown mode
6. Q3 B) Attempt any two question. [10M]
   • i) Draw the logic circuit of an R-S flip flop using NOR gates and write down its state transition
   • ii) Draw neat labeled diagram for master J-K flip flop and give its truth table ili) Explain the concept of Serial in serial out shift register (SISO)
   • iv) Give classification of different types of counters
7. Q4 Attempt any three questions. [15M]
   • i) What do you understand by stabilization of the operating point? What is the definition of li) Determine the open circuit voltage of the source, v, to provide an amplifier input voltage v; of
   • 0.25 V when the internal resistance of the source is 50 ohms
   • iii) In an inverting op-amp as an adder find the output voltage assuming the Op-Amp is initially nulled. If R2=3KQ, & R=10KQ for three input voltages V;=0.5V ,V2= -5.5
   • iv) Write a note on the comparator
   • v) Differentiate between latch & flip flop
   • vi) What is the counter? What is meant by a serial counter and parallel counter?

Read from the scan above, so a character or two may differ. The scan is the original.