B.Sc. (Computer Science) Digital System and Architecture Syllabus - Mumbai University
This is the FY BSc Computer Science syllabus under NEP 2020, in force from the academic year 2024-25. The University still sets the earlier Choice Based papers alongside it — her Summer 2026 third-year timetables name that scheme — so check which scheme your exam form names before you revise.
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Syllabus for Digital System and Architecture
MU’s credit structure table for this programme calls this course “Digital Systems & Architecture”. The title above is the one she prints on the syllabus itself; both name the same course.
The University sets the practical for this subject separately, in Computer Science Practical 1, as Module 1. It carries its own credits, so it is examined as a paper of its own.
Module I
- Fundamentals of Digital Logic: Boolean algebra, Logic Gates, Simplification of Logic Circuits: Algebraic Simplification, Karnaugh Maps.
- Combinational Circuits: Adders, Subtractors, Multiplexer, De-Multiplexer.
- Sequential Circuits: Flip- Flops (SR, JK & D), Counters: synchronous and asynchronous Counter.
- Computer System: Comparison of Computer Organization & Architecture, Computer Components and Functions, Interconnection Structures. Bus Interconnections, Input / Output: I/O Module Programmed I/O, Interrupt Driven I/O, Direct Memory Access.
Module II
- Memory System Organization: Classification and design parameters, Memory Hierarchy, Internal Memory: RAM, SRAM and DRAM, Interleaved and Associative Memory. Cache Memory: Design Principles, Memory mappings, Replacement Algorithms, Cache performance, Cache Coherence. Virtual Memory, External Memory: Magnetic Discs, Optical Memory, Flash Memories, RAID Levels
- Instructions: Instruction Formats, Instruction Sets, Addressing Modes, Addressing Modes Examples with Assembly Language [8085/8086 CPU].
- Processor Organization: Structure and Function. Register Organization [8085/8086 CPU]. Basic Microprocessor operations: Data Transfer (Register / Memory) Operations, Arithmetic & Logical Operations.
- Instruction Cycle, Instruction Pipelining. Introduction to RISC and CISC Architecture, Instruction Level Parallelism and Superscalar Processors, Design Issues.
Text Books
- 1 M. Mano, Computer System Architecture 3rd edition, Pearson
- 2 Carl Hamacher et al., Computer Organization and Embedded Systems, 6 ed., McGraw-Hill 2012
- 3 R P Jain, Modern Digital Electronics, Tata McGraw Hill Education Pvt. Ltd. , 4th Edition, 2010
- 1 William Stallings (2010), Computer Organization and Architecture- designing for performance, 8th edition, Prentice Hall, New Jersy.
- 2 Anrew S. Tanenbaum (2006), Structured Computer Organization, 5th edition, PearsonEducation Inc,
- 3 John P. Hayes (1998), Computer Architecture and Organization, 3rd edition, Tata McGrawHill
- 4 Ramesh Gaonkar (2013), Microprocessor Architecture, Programming and Application with 8085, 6 th edition, Penram.
Reproduced from the University of Mumbai syllabus for B.Sc. (Computer Science) under NEP 2020, in force from the academic year 2024-25. Wording is as printed in that syllabus. Module numbering is as printed there too.