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Engineering B.E. (Computer Engineering) Sem 3 Digital Logic and Computer Architecture May 2023 Question Paper - Mumbai University | munotes

Digital Logic And Computer Architecture Question Paper, May 2023.pdf
CMPN · 1 May 2025

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Questions asked in this paper

  1. Q2 Attempt any three questions from remaining five questions
  2. Q3 Assume suitable data if necessary and justify the assumptions
  3. Q4 Figures to the right indicate full marks
  4. Q1 147 in to binary i1) in to Decimal i11) (135)g in to decimal
    • iv) 234 in to BCD
    • v) 23 in to gray code Write a short note on Encoder 05 Differentiate between Hardwired control unit and Micro programmed control unit 05 D Differentiate between SRAM & DRAM 05
  5. Q2 Draw the flow chart of Non Restoring division algorithm and Perform 4 +2 Explain Flynn’s classification 10 10 marks
  6. Q3 Explain the instruction cycle with the help of a neat state diagram Explain the various addressing modes 10 Represent -786.25 using IEEE standards (both single and double precision 10 10 marks
  7. Q5 Explain different memory Mapping Techniques List & Explain the Characteristics of Memory 05 C What do you mean by cache coherence 05 10 marks
  8. Q6 Draw and explain 4 stage instruction pipelining and briefly describe the hazards associated Describe various Bus Arbitration methods 10 10 marks

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