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Engineering B.E. (Computer Engineering) Sem 3 Digital Logic Design and Analysis May 2024 Question Paper - Mumbai University | munotes

Digital Logic Design And Analysis Question Paper, May 2024.pdf
CMPN · 1 May 2025

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Older exam None: this is the earliest we hold
Newer exam None yet: this is the latest New papers land after each exam season.

Questions asked in this paper

  1. Q2 a. Explain the uses of grey code. 5 marks
    • b. Convert JK f/f into D f/f. 5
  2. Q4 a. Solve using K map and implement using NAND gates only
    • b. Explain 4 bit bidirectional shift register. 10
  3. Q5 a. Write Short note on Priority Encoder. 5 marks
    • b. Sate and prove De Morgan’s theorem. 5
  4. Q6 a.Compare synchronous and asynchronous counters. 5 marks
    • b. Implement full adder using 3 to 8 decoder and NAND gates. 5
    • c. Explain Master Slave JK flip flop in detail. 10

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