Combinational and Sequential Design Notes | B.Sc. (Information Technology) Semester 1 | Mumbai University | munotes

Contents

Module I 1. Study of Logic gates and their ICs and universal gates:

1. How This Paper Is Examined, and How to Read This Book 1
2. The Bench: Breadboard, Power Supply and the Five Volt Rail 3
3. Reading a DIP: Pin One, the Notch, and the Chips That Break the Rule 6
4. Switches, LEDs and the Logic Probe 9
5. Wiring a Circuit That Works the First Time 12
6. When It Does Not Work: Finding the Fault 15
7. Bits, and Why a Digital Circuit Has Only Two Voltages 18
8. Binary, Decimal, Octal and Hexadecimal 20
9. Converting Between the Bases 23
10. Binary Addition and Subtraction 25
11. Signed Numbers, and the Two Complements 28
12. BCD: the 8421 Code 31
13. Excess-3, and Why It Is Self-Complementing 34
14. Gray Code, and Why Exactly One Bit Changes 37
15. The Three Basic Gates: AND, OR and NOT 40
16. NAND and NOR 43
17. XOR and XNOR 46
18. Positive Logic, Negative Logic and the Bubble 49
19. TTL: What a 1 and a 0 Really Are 52
20. The 7400, 7408, 7432 and 7404 55
21. The 7402, and Its Reversed Pins 58
22. The 7486 and the 74266, Which Needs a Resistor 61
23. Testing a Gate IC Before You Trust It 64
24. Boolean Algebra: the Postulates 67
25. The Laws: Commutative, Associative and Distributive 70
26. The Theorems: Idempotence, Absorption and Consensus 73
27. Duality, and What It Saves You 77
28. De Morgan's Two Laws 80
29. Verifying De Morgan on the Bench 84
30. Simplifying an Expression by Algebra 88
31. The Truth Table as the Statement of a Problem 92
32. Minterms and the Sum of Products 96
33. Maxterms and the Product of Sums 100
34. Moving Between SOP, POS and the Table 104
35. The Karnaugh Map: Why Gray Order Makes It Work 107
36. Two and Three Variable Maps 111
37. The Four Variable Map 115
38. Grouping: Prime Implicants and Essential Prime Implicants 119
39. Don't-Care Conditions 123
40. Reading a Product of Sums Answer Off the Map 127
41. When the Map Gives Two Answers 131
42. NAND Is Universal 135
43. Building the Five Gates from NAND 139
44. NOR Is Universal 143
45. Building the Five Gates from NOR 146
46. Converting an SOP Circuit to All-NAND 150
47. Converting a POS Circuit to All-NOR 154
48. Implementing an Expression with the Fewest Gates 157
49. The Fewest ICs, Which Is a Different Question 161
50. Designing a Combinational Circuit from Words 165
51. A Worked Design, End to End 168
52. A Second Worked Design, in POS Form 172
53. What a Code Converter Is 177
54. Binary to Gray Code Converter 181
55. Gray to Binary Code Converter 184
56. Binary to BCD Code Converter 187
57. Binary to Excess-3 Code Converter 191
58. The Half Adder 194
59. The Full Adder 197
60. The Four Bit Ripple Carry Adder 200
61. The Half and Full Subtractor 204
62. Subtraction by Complement, and the Adder-Subtractor 208
63. The BCD Adder 211
64. The BCD Subtractor 215
65. The Excess-3 Adder 219
66. The Excess-3 Subtractor 222

Module II 6. Implement Arithmetic circuits.

1. Arithmetic Circuits Beyond the Adder 225
2. Multiplying in Binary by Hand 228
3. The Two by Two Binary Multiplier 231
4. Comparing Two Bits 235
5. The Two Bit Magnitude Comparator 238
6. Cascading Comparators, and the 74266 242
7. The Data Path Family 245
8. What an Encoder Does 248
9. The Eight to Three Encoder 250
10. The Priority Encoder 254
11. What a Decoder Does 257
12. The 2-to-4 and 3-to-8 Decoder from Gates 260
13. The 74138 263
14. The 74139 266
15. What a Multiplexer Does 269
16. The Four to One Multiplexer from Gates 272
17. The 74153 276
18. The 74157 279
19. What a Demultiplexer Does 282
20. The One to Four Demultiplexer 285
21. The 74151 288
22. Realising a Three Variable Function on a 74151 291
23. Realising a Four Variable Function on a 74151 295
24. Realising a Function on a 74138 299
25. Combinational Against Sequential 303
26. The SR Latch from NOR Gates 307
27. The SR Latch from NAND Gates 311
28. The Gated Latch and the D Latch 314
29. Level Triggering, Edge Triggering and Master-Slave 317
30. The SR Flip-Flop 321
31. The D Flip-Flop 324
32. The JK Flip-Flop, and the Race Around 327
33. The T Flip-Flop 330
34. Characteristic Tables and Excitation Tables 333
35. The 7473 336
36. The 7474 340
37. The 7476 343
38. Converting SR to JK, D and T 346
39. Converting JK to D, T and SR 349
40. Converting D to T and T to D 352
41. What a Counter Is 355
42. The Three Bit Ripple Counter with the 7473 358
43. Propagation Delay, and Why Ripple Counters Glitch 361
44. Designing a Synchronous Counter 365
45. The Three Bit Synchronous Counter with the 7473 369
46. An Up-Down Counter, and a Counter with a Gap 372
47. Mod-N Counters 376
48. Mod-N Counters from the 7473 and 7400 380
49. The 7490 384
50. The 7492 and the 7493 388
51. Mod-N Counters from the 7490, 7492 and 7493 392
52. Cascading Counters Past Ten 396
53. Registers and What They Hold 399
54. The Serial In, Serial Out Register 402
55. The Serial In, Parallel Out Register 405
56. The Parallel In, Serial Out Register 408
57. The Parallel In, Parallel Out Register 411
58. The Bidirectional Shift Register 414
59. The 7495 417
60. Ring Counters and Johnson Counters 420
61. The Seven Segment Display 424
62. Designing the Seven Segment Decoder by K-Map 427
63. The 7447 431
64. Simulating Before You Wire 435

Module J The certified journal, the two-hour practical examination, the viva and the internal assessment

1. The Journal, and Why It Decides Whether You Sit the Exam 438
2. Writing Up One Practical, Completely 441
3. The Two Hour Practical Examination 444
4. The Viva: the Questions That Are Actually Asked 447
5. The Internal Twenty Marks 451