B.E. (Computer Engineering) Computer Organization and Architecture Syllabus - Mumbai University 2026

The University has moved this degree onto NEP 2020 one year at a time. The first and second years are NEP 2020 syllabi; the third and fourth years are still examined on the REV-2019 'C' Scheme, which is what the University sets for them this year.

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Syllabus for Computer Organization & Architecture

Semester 3 · Second Year CE · 3 credits · 100 marks

Module 1: Computer Fundamentals

Number Systems: Binary. Octal and Hexadecimals. Binary Number representation: Sign Magnitude, 1’s and 2’s Compliment representation. Logic Gates: AND, OR, NOT, NAND, NOR, EX OR. Basic Organization of Computer, Von Neumann model.

Module 2: ALU Operations

ALU Operation: Addition and Subtraction on Binary, Octal, Hexadecimal number. Booth’s Algorithms, Restoring and Non restoring division algorithm. IEEE 754 Floating point representation and conversation.

Module 3: Processor Organization and Control Unit Design

8086 Processor: Architecture of 8086 processor, Register Organization, Instruction formats, instruction cycle, addressing modes. Control Unit: Instruction interpretation and sequencing, Micro-programmed and hardwired control unit design methods. Microinstruction sequencing and execution, Micro programs. RISC and CISC: Introduction to RISC and CISC architectures and design issues.

Module 4: Memory Systems Organization

Introduction to Memory and Memory parameters. Classifications of primary and secondary memories. Types of RAM and ROM, Memory hierarchy and characteristics, Virtual Memory: Segmentation and Paging Cache memory: Concept, hierarchy (L1, L2, L3), mapping techniques. Cache Coherency and technique to resolve it. Interleaved and Associative memory. Self-Study : Case study of Pentium Processor Cache Memory Model (MESI Protocol)

Module 5: I/O Organization

Buses: Types of Buses, Bus Arbitration, Bus standards and its comparative study I/O Interface, I/O channels, I/O modules and IO processor, Types of data transfer techniques: Programmed I/O, Interrupt driven I/O and DMA.

Module 6: Parallel Processing

Advanced Processor Models(80386DX): Real Model, Protected Model, Virtual Model Pipelined Architecture: Pipeline Stages, Superscalar architecture Pipeline Hazards, Mitigation of Hazards with branch prediction and data forwarding techniques, Amdahl’s Law Introduction to parallel processing concepts, Flynn’s classifications. Self-Study: Superscalar Architecture: Case study of Pentium processor and GPGPU architecture.

Text Books

1 Modern Digital Electronics 4th R P Jain Tata McGraw-Hill 2009
2 Computer Organization 5th Carl Hamacher, Tata McGraw-Hill 2002 Zvonko Vranesic
3 Computer Architecture and 3rd John P. Hayes Tata McGraw-Hill 2012 Organization
4 Computer Organization and 8th William Stallings Pearson 2010 Architecture: Designing for Performance
5 Microprocessors and Interfacing 3rd Douglas V Hall Tata McGraw-Hill 2017
6 The 80386, 80486, and Pentium 3rd Walter Triebel Pearson 1997 Microprocessor: Hardware, Software, and Interfacing
7 Pentium Pro Processor System 3rd Tom Shanely Addison Wesley 1996 Architecture Sr. No Title Editi Authors Publisher Year on
1 Structured Computer Organization 6th Andrew S. Pearson 2012 Tanenbaum
2 Computer Architecture and 2nd B. Govindarajulu McGraw Paperba Organization: Design Principles and Hill ck-2017 Applications
3 Advance Computer Architecture: 3rd Kai Hwang Tata- 2017 Parallelism, Scalability, McGraw Programmability Hill
4 Microcomputer System 2nd Liu and Gibson Pearson 2015 The 8086/8088 family
5 Programmer’s reference Manual for 1st Steven Armburst Tata IBM Personal Computers McGraw Hill

Reproduced from the University of Mumbai syllabus for B.E. (Computer Engineering) under NEP 2020, in force from the academic year 2025-26. Wording is as printed in that syllabus. Module numbering is as printed there too.

The complete syllabus

This subject is cut from the University circular for its year. Open a document here if you want the whole thing rather than a single subject.

PDF 7.9 (R-A) B.E. (Computer Engineering) Sem I & II (Revised, NEP 2020) NEP 2020 syllabus Read full PDF Read

PDF 6.24 (N) B.E. (Computer Engineering) Sem III & IV (NEP 2020) NEP 2020 syllabus Read full PDF Read

PDF 6.15 B.E. (Computer Engineering) Third Year, Sem V & VI (REV-2019 'C' Scheme) REV-2019 'C' Scheme syllabus Read full PDF Read

PDF 6.41 (R) B.E. (Computer Engineering) Fourth Year, Sem VII & VIII (REV-2019 'C' Scheme) REV-2019 'C' Scheme syllabus Read full PDF Read

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