USIT202-Microprocessor-Architecture-munotes

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UNIT 1
1
MICROPROCESSOR, MICROCOMPUTERS,
AND ASSEMBLY LANGUAGE
Unit Structure
1.0 Objectives
1.1 Introduction
1.2 Microprocessor
1 . 2 . 1 A P r o g r a m m a b l e M a c h i n e
1 . 2 . 2 A d v a n c e s i n S e m i c o n d u c t o r T e c h n o l o g y
1 . 2 . 3 O r g a n i z a t i o n o f a M i c r o p r o c e s s o r - b a s e d s y s t e m
1.2.4 How does the Microprocessor work"
1.3 Microprocessor Instruction Set and Computer Languages
1 . 3 . 1 M a c h i n e L a n g u a g e
1.3.1.1 8085 Machine language
1 . 3 . 2 A s s e m b l y l a n g u a g e
1.3.2.1 8085 Assembly language
1.3.2.2 Writing and executing an assembly language program
1 . 3 . 3 H i g h - l e v e l l a n g u a g e
1 . 3 . 4 O p e r a t i n g s y s t e m s
1.4 From Large Computers to Single-Chip Microcontrollers
1 . 4 . 1 L a r g e c o m p u t e r s
1 . 4 . 2 M e d i u m - s i z e c o m p u t e r s
1 . 4 . 3 M i c r o c o m p u t e r s
1.5 Application:
1 . 5 . 1 S y s t e m h a r d w a r e
1 . 5 . 2 S y s t e m s o f t w a r e
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2MICROPROCESSOR ARCHITECTURE
1.6 Summary
1.7 List of references
1.8 Unit End Exercise
1.0 Objectives
After going through this chap ter, you will be able to
x Define microprocessor
x Define microprocessor based s ystem and functions of each compon ent
x Differentiate between machine language, assembly language and h igh-level
language
x Classification of computers
x Design of basic microprocessor c ontrolled temperature system (M CTS)
application
1.1 Introduction
x Today microprocessor systems are used in every sphere of life w ith day to
day demand increasing for faster and better systems.
x Microprocessors are multipurpose versatile devices that are des igned either
for generic or specifi c functionalities.
x Microprocessor is the brain of com puter which does all the work .
x Before we start a detailed study about the microprocessors, we need to know
the differences between the following:
¾ Microcomputer – A computer with a microprocessor as its CPU and
includes memory, I/O
¾ Microprocessor –A silicon chip which includes ALU, register circuits
& control circuits
¾ Microcontroller –Also a silicon chip which includes microprocessor,
memory & I/O all in a single package.

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3Chapter 1: Microprocessor, Microcomputers, and Assembly Languag e
1.2 Microprocessor
x The term microprocessor is an amalgamation of two words - micro and
processor.
x Processor means a device that processes data or information but i n t h i s
perspective it will process only binary data 0s and 1s.
x The word micro is the latest addition.
x In early 1960s, the processor was built using separate elements and in the
1970s all of the components that make up the processor are fabr icated on a
single chip i.e. silicon chip.
x So this reduces the size of the processor and increases the com putation speed.
x So we can now say that Microprocessor is born.
Definition : Microprocessor is a multipurpose re gister-based clock-driven device
that takes binary data as input, processes it according to instructions stored in its
memory, and provides binary results as output.
x A microprocessor is the central processing unit of a computer s ystem and is
processes the distinctive set of instructions and programs
x The microprocessor is made up of several tiny components namely diodes,
transistors and registers that work together .
x The microprocessor is a programmable device that takes in data and performs
arithmetic or logical operations on them based on the instructi ons and
program stored in memory and then produces processed results.
x We elaborate underlined words in depth.
x As a programmable device, the microprocessor performs different
operations on the data based on the instruction given to carry out the task.
The microprocessor manipulates it by changing the operation car ried out by
the instruction.
x The data the microprocessor takes in for manipulation comes from the input
devices. These devices writes data from the outside world to th e
microprocessor.
x The microprocessor only understands binary data or numbers. A b inary
number is called a bit. The microprocessor identifies and manip ulates these
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x Every microprocessor has basic arithmetic operations s u c h a s a d d i t i o n ,
subtraction, increment and decrement and logic operations such as 1OT,
OR, A1D, E;OR, shifting (left or right).
x Memory is the location where instructions and programs are stored . Each
location is capable of storing only one bit. So several bit loc ations are
combined to create registers and several registers are combined to create a
memory. Each location in memory is identified by address and ca pable of
storing group of bits.
x After manipulation the microprocessor produces results and sends it to the
output device. These devices display the results to the outside world reading
it from the microprocessor.
1.2.1 A Programmable Machine
x A typical programmable machine has four parts that work collect ively.
x Hardware is the physical part of the system.
x Set of instruction is the program that instructs the microproce ssor to perform
the required operation and set of programs makes the software.

Figure 1.1 – A Programmable Machine
x The microprocessor is the central unit of a computer system tha t performs
basic arithmetic and logic operation .
x A microprocessor works on the instructions stored in memory by accepting
binary data as input followed by processing the data and then p roduces
output.

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x The microprocessor applications are classified into two categor ies
¾ Reprogrammable system –The microprocessor computes and processes
instructions given by the user or programmer.
¾ Embedded system – T h e p r o g r a m m i n g i s a l r e a d y d o n e a n d
microprocessor is part of the specific system such as washing m achine,
fridge and air conditioner.
x The microprocessor processes on binary digits (called bits) i.e . 0 and 1 only.
x Several digits i.e. bits are combined to create words and this forms the basis
of microprocessor classif ication based on word length.
x The memory stores instructions and data in group of bits.
x This information is given to the microprocessor whenever it is required..
x Memory is viewed as pages in notebook where each line represent s register
and is capable of storing a binary word.
x So for example each line is an 8 bit register that stores a 8 b it word and several
registers are combined one below the another to create a memory cell.
x The combination of registers to create a memory cell is always in power of
two.
x The user enters data into memory through input devices like key board and
simple switch.
x The microprocessor reads the instruction from the memory and pr ocesses the
data according to those instructions.
x The results are viewed on output device like seven segment LEDs and printer.
He[adecimal keyboard Switches Seven segment LED Printer Figure 1.2 – Input and Output Devices
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1.2.2 Advances in Semiconductor Technology
x Semiconductor technology has undergone unprecedented changes fr om its
inception in 1950s
x In early systems the semiconductor devices have replaced vacuum t u b e s
which drastically reduced the size of the system.
x The invention of transistors further brought down the size of t he system
x SSI (Small Scale Integration) containing upto 10 transistors were used in
development of early systems.
x The number of transistors slowly increased to about 100 calling i t MSI
(Medium-Scale Integration).
x By 1970s tens of thousands of transistors were used calling it LSI (Large
Scale Integration) system.
x Later on hundreds of thousands of transistors on a single chip brought in the
VLSI (Very Large Scale Integration) era.
x Today we are in the era of SLSI (Super Large Scale Integration).
Historical Perspective:
x The world’s first recognized microprocessor is Intel4004 a 4-bit
microprocessor –programmable controller on a chip.
x There were just 45 instructions for 4004 and widely used in vid eo games and
small-scale microprocessor control system.
x The instructions executed at 50KIPs (kilo-instructions per seco nd) and
fabricated with P-Channel MOSFET (Metal Oxide Semiconductor Fie ld
Effect Transistor).
x In 1970 due to the increase in computational demand, Intel buil t the 8008
which is extended 8-bit version of the 4004 microprocessor.
x As people begin to use, Intel recognized the limitations and ca me up with the
powerful 8 bit microprocessor 8080 in 1973.
x Several other manufacturers too e ntered the microprocessor mark et.
x Table 1.1 lists several of these early microprocessors and thei r manufacturers.

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Table 1.1 – Early Microprocessor Manufacturer Part Number Fairchild F-8 Intel 8080 MOS Technology 6502 Motorola MC6800 1ational Semiconductor IMP-8 Rockwell International PPS-8 =ilog =-8
x With fifty years since the invention of the 4004, Intel has mad e the processors
that are designed with 15 million transistors that can address 1TB of memory
and can operate at 400 Mhz to 1.5 GHz frequency.
x The following table summarizes the historical perspective of In tel
microprocessors.
Table 2 – Intel Microprocessor Historical Perspective Microprocessor Year of Introduction Data Bus Address Bus 4004 1971 4 8 8008 1972 8 8 8080 1974 8 16 8085 1977 8 16 8086 1978 16 20 80186 1982 16 20 80286 1983 16 24 80386 1986 32 32 80486 1989 32 32 Pentium 1993 onwards 32 Core Solo 2006 32 Dual Core 2006 32 Core 2 Duo 2006 32 4uad Core 2008 32 i3, i5, i7 2010 64 munotes.in

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1.2.3 Organi]ation of A Microprocessor-Based System
x The organization of a microprocessor based system consist of th ree basic
components: microprocessor, I/O and memory.
x These components are organized around a common communication pa th
called a bus.

Figure 1.3 – Microprocessor-Based System with Bus Architecture
x Microprocessor: A typical microprocessor consists of three sub components
namely arithmetic and logic unit (ALU), control unit and regist er array to
process the instructions.
¾ Arithmetic and Logic Unit : The ALU performs the arithmetic and
logical operations such as Addition, Subtraction, A1D, OR, ;OR etc.
The data is taken from memory, accumulator and registers to per form
operation. The results of the operations in the microprocessor are
usually stored in the accumulator or memory.
¾ Register Array: T h e 8 0 8 5 m i c r o p r o c e s s o r i n c l u d e s s i x g e n e r a l -
purpose registers, one accumulator and one flag register. It al so has two
16-bit registers namely stack pointer and program counter.
¾ Control unit: It provides timing and control signal to the
microprocessor to perform operations such as read and write fro m
memory and peripherals.
x Memory: It stores information in binary format. The user enters its
instructions into the memory. The microprocessor reads these in structions
stored in the memory in sequence, interprets and executes one b y one and
stores the final results in memory or sends it to output device . The
microprocessor contains basically two types of memory.
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¾ Read Only Memory (ROM) – A nonvolatile memory that stores
information that does not change.
¾ Random Access Memory (RAM) or Read/Write Memory – A
volatile memory that stores information supplied by the user su ch as
programs and data.
x I/O Devices: I/O (Input/output) devices also referred as peripherals. The
input device is a hexadecimal keyboard with some additional fun ctional keys
to perform. The output device is a 7 segment LED display which displays the
processed results.
x System bus: It is a set of wires that establishes communication or connect ion
between the microprocessor and peripherals to exchange data. Th ere are three
types of system bus
¾ Address bus
¾ Data bus
¾ Control bus
1.2.4 How Does The Microprocessor Work"
x To execute a program, the microprocessor reads the instruction from the
memory, interprets and decodes it, then executes it.
x The instructions are sequentially stored in the memory one afte r another.
x So the microprocessor fetches the first instruction from the me mory,
interprets and executes that instruction.
x The series is continued until each and every instructions are d one.
x The microprocessor uses system bus to fetch the address, data a nd binary
instructions to and from the memory.
x It uses registers to store data temporarily, performs the opera tions in ALU
and sends the binary result to seven segment LEDs.
1.3 Microprocessor Instruction Set and Computer Languages
x Microprocessor processes binary words.
x However each microprocessor has its own binary words creating t he
instruction set and the interpretation of the words which is de signed based on
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x The word length (expressed in bytes – 8 bits) is defined as the number of bits
the microprocessor recognizes and processes in a given time
x To communicate with the computer one must give instruction in b inary
language or machine language .
x It is difficult for most people to write programs in binary for mat.
x So programmers write program in assembly language which contain English
like word to represent the bina ry instruction of a machine.
x But assembly programs are specific to given machine and cannot be
transferred from one machine to another.
x So high level languages are used which contains English like statements and
are machine independent.
1.3.1 Machine Language
x The number of bits in a word for a given language is fixed and the words are
formed through various combinations of these bits.
x If a machine language has ‘n’ bits then the language has 2n words.
x For example a machine with a word length of eight bits can have 256 (28)
combinations of eight bits – thus a language have 256 words.
x The design engineer selects only certain combination of bit pat tern and not
all and then gives a specific interpretation to each combinatio n known as
instruction.
1.3.1.1 8085 MACHINE LANGUAGE
x The Intel 8085 is an 8-bit microprocessor with 246 identifiable patterns
forming 74 instructions.
x It is difficult to enter the instructions in binary and hence e ntered in
hexadecimal code format.
x For example, the combination 0000 1100 (Hex Code – 0C) is interpreted as
Increment the value of Register C by 1.
x It is tedious and error-inducive for people to write instructio ns in binary
language so writing in hexadecimal makes it less error-prone.

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1.3.2 Assembly Language
x Entering the instructions using hexadecimal is quite easier tha n entering the
binary combinations.
x But just reading a set of hexadecimal code makes it difficult f or the user to
interpret the meaning of the program.
x So the designers of the microprocessor give symbolic name for e ach
hexadecimal code.
x This code known as mnemonics are short English words which are machine
dependent.
x The assembly language program written for one type of microproc essor is
not transferable to a computer with another microprocessor unle ss the
machine codes are compatible with each other.
1.3.2.1 8085 ASSEMBLY LANGUAGE
x The complete set of 8085 mnemonics is called the 8085 assembly language
program.
x Using the same example from before, 0000 1100 is 0C in hex and the
mnemonic is I1R C.
x It is important to remember that a machine language and its ass ociated
assembly language are completely machine dependent.
x For example, an 8-bit microprocessor for Motorola i.e. 6800 an d Intel i.e.
8085s instruction sets are different from each other.
x So a program written for the 6800 microprocessor cannot be exec uted on
8085 microprocessor and vice versa.
1.3.2.2 Writing and E[ecuting an Assembly Language Program
x There are two ways to accomplish this task.
x The first procedure is called either manual or hand assembly. The steps are
¾ From the instruction set given by the manufacturer, write the
instructions in assembly language.
¾ Find the corresponding hexadecimal code for each instruction.
¾ Enter the hex code in the memory step by step in the kit using the
hexadecimal keyboard.
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¾ Correct errors if any and view the result in seven segment LED Display.
x Another technique is the use of assembler tool.
¾ The assembler is a tool that translates the mnemonics or hex co de into
the corresponding binary machine codes of the microprocessor.
¾ Each microprocessor uses its own assembler because the mnemonic s
and machine codes are specific to the microprocessor, and each
assembler has its own set of conversion rules that must be foll owed by
the user.
1.3.3 High-Level Language
x They are programming language which are machine-independent
x They have English like statements with proper syntax and semant ic.
x The machine does not understand high level language and so tool s like
compiler and interpreter convert t hem into machine language for processing.
x Example BASIC, C, C and Java

Figure 1.4 – Translation of High-level Language
Program into Machine Code

1.3.4 Operating Systems
x The operating system controls the overall operation and manages t h e
interaction between the computer hardware and software.
x It is basically a collection of programs.
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Figure 1.5 – Functional Relationship of Operating System
with System Hardware

x The operating system helps in communication between the memory and
peripherals and stores the information on the disk.
x The operating system boots when the system is switched on ident ifying the
hardware and handles the appli cation programs running in the ba ckground.

Figure 1.6 – Hierarchical relationship of operating system
with hardware software
x Several operating systems have evolved over the years from cont rol monitor
program to graphical user interface operating system.
x Example MS-DOS, Unix, Linux, Os/2, Windows 95/98/2000/ME/7/7/1/ 10

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1.4 From Large Computers to Single-Chip Microcontrollers
x Depending on the needs of the user, computers are classified an d designed
for different purpose.
x Initial classification of computer s was mainframe, mini compute rs and
microcomputers.
x With changes in technology and microprocessor being part of eve ry computer
the new classification includes large computer, medium size com puter and
microcomputers.
1.4.1 Large Computers
x General purpose multitasking multi user computers are called la rge
computers.
x They are capable of solving complex and scientific calculations and handles
huge volumes of data and handles hundreds of user.
x Based on size they are classified into
¾ Mainframe – High speed computers to handle large count of users.
Example IBM System/390 series.
¾ Supercomputer – High speed and high performance computer used in
research. Example Cray-2 and <-MP.
Mainframe Supercomputer Figure 1.7 - Large Computers
1.4.2 Medium-Si]e Computers
x To meet the needs of small factories and data processing tasks the medium-
size or mini computers are introduced.
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x Multi processing system capable of supporting hundreds of users but
technology is different as these machines are slow and memory s ize is less
than mainframe.

Figure 1.8 - Mini Computer
1.4.3 Microcomputers
x It contains microprocessor as its central processor along with memory and
minimal input/output devices
x Most powerful in 1970s and in 1980s with advent of increasingly powerful
microprocessors more widely used.
x They are classified into four categories –
¾ Personal computer (PC) – A small computer designed for single
user and is relatively inexpensive. The entire processor is on single
chip and used in word processing, accounting, personal finance ,
desktop publishing, accessing resources on the Internet.
¾ Workstations - It is similar to PC but a powerful processor that suites
for engineering and scientific a pplications, software developme nt and
specific applications seeking a verage computing power and high- end
graphics.
¾ Single-board microcomputer – It is used in small industries and
college labs to understand, evaluate and test the performance o f specific
microprocessor. All basic components such as memory, keyboard,
LED are there with the 8 or 16 bit microprocessor.
¾ Single-chip microcomputers – I n c l u d e s a m i c r o p r o c e s s o r , R / W
Memory, Read Only Memory and I/O Devices on single chip and
hence commonly referred as microcontrollers.
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Personal Computer Workstation Single-board
microcomputer Single-chip
microcomputer Figure 1. – Types of micro computers
1.5 Application – Microprocessor Controlled Temperature
System (MCTS)
x We are building a microprocessor controlled temperature system that is
capable of reading the temperature in a room and display the re corded
temperature in LCD (Liquid Crystal Display) and based on the va lue turn on
the fan if the temperature is high or turn on the heater if tem perature is low
based on the set point value

Figure 1.10 – MCTS
1.5.1 System Hardware
x The hardware part of the applicat ion comprises of the following
components
¾ Microprocessor – T h e j o b o f t h e p r o c e s s o r i s c o n t r o l t h e o v e r a l l
communication. It reads instructi ons from memory, interprets an d
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executes them. It reads temperature from LCD and turn on/off fa n or
heater depending on the set point value
¾ Memory – The ROM provides instructions to monitor the system and
R/W memory temporary stores the temperature value.
¾ Input Device – The temperature sensor is the main input device which
measures the temperature in signals and for the microprocessor to
process the signal A/D (Analog to Digital) Convertor is used. D evices
cannot be directly connected to processor and therefore connect ed via
input ports.
¾ Output Device – LCD panel, fan and heater forms the output device of
this application. Just as input device cannot be directly conne cted, the
output devices are also connected via ports.
1.5.2 System Software
x The system is initially reset and microprocessor reads instruct ions from the
memory one by one, decodes it and then executes it.
1.5 Summary
x The microprocessor is an important component of a digital compu ter.
x The microprocessor along with memory and I/O devices carry out various
functionalities.
x The 8085 is a powerful microprocessor.
x Different computer languages are available but the processor un derstands the
machine language and users program in assembly or high level la nguage
x Various classification of systems are available today but micro processor is
an integral part of these systems
x In designing a microprocessor based system, the hardware and so ftware part
have to be designed concurrently because of the interdependenc y.
List of References
x Ramesh Gaonkar “Microprocessor Architecture, Programming and
Applications with the 8085”, Fifth Ed ition, Penram International Publishing
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x B. Ram, “Fundamentals of Microprocesso r and Microcomputers”,. Sixth
Revised and Enlarged Edition, Dha npat Rai Publications (P) Limi ted
x Barry B. Brey, “The Intel Microprocessors - Architecture, Programming, and
Interfacing”, Eight Edition, Pearson Prentice Hall
x https://www.tutorialspoint.co m/microprocessor/microprocessorBov erview.h
tm
Unit End E[ercise
1. What are the essential components of a microprocessor based sys tem" Draw
the block diagram and explain the function of each component.
2. What is a microprocessor" What is the difference between a micr oprocessor
and CPU"
3. Explain the various I/O devices used along with a microprocesso r.
4. Explain the types of computer languages. What are the advantage s of an
assembly language over the high level language"
5. What is an operating system" Explain its functional and hierarc hical
relationship with various hardware components.
6. Differentiate between personal computer, workstation, single-bo ard and
single-chip microcomputers.

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UNIT 1
2
MICROPROCESSOR ARCHITECTURE AND
MICROCOMPUTER SYSTEMS
Unit Structure
2.0 Objectives
2.1 Introduction
2.2 Microprocessor Architecture and its Operation
2 . 2 . 1 M i c r o p r o c e s s o r - I n i t i a t e d O p e r a t i o n s
2.2.2 Internal Operations
2 . 2 . 3 P e r i p h e r a l O p e r a t i o n s
2.3 Memory
2 . 3 . 1 F l i p - f l o p o r L a t c h a s S t o r a g e E l e m e n t
2.3.2 Memory Map and Address
2 . 3 . 3 W o r d S i z e o f M e m o r y
2.3.4 Instruction Fetch from Memory
2.3.5 Classification of Memory
2.4 I/O Devices
2 . 4 . 1 P e r i p h e r a l - m a p p e d I / O
2 . 4 . 2 M e m o r y - m a p p e d I / O
2.5 Microcomputer System Illustration
2.6 Logic Devices
2.6.1 Tri-state Device
2.6.2 Decoder
2 . 6 . 3 E n c o d e r
2 . 6 . 4 D F l i p - f l o p
2.7 Application: MCTS
2.8 Summary
2.9 List of references
2.10 Unit End Exercise

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2.0 Objectives
After going through this chap ter, you will be able to
x Understand and identify the operations performed by the micropr ocessor
x Recognize the memory organization
x Learn to create the memory map and address range
x Understand the types of memory available
x Identify the ways to communicate with I/O Devices
x Know the need of logic devices for interfacing
2.1 Introduction
x The microprocessor is a programmable digital device designed wi th flip-flop,
registers, buffers and several other tiny element all which is integrated on a
single chip.
x To establish communication between these elements, each micropr ocessor
has its own instruction set.
x The instruction set of the microprocessor is designed to help p erform data
manipulation and communication.
x The architectural and logic desi gn of the microprocessor helps in executing
these instructions to obtain the desired result.
2.2 Microprocessor Architecture and its Operation
x User can write programs using the instruction set of the microp rocessor.
x We can program the microprocessor to do variety of functions.
x So the above functions are categorized into three categories na mely
Microprocessor initiated operati ons, Internal operations, Perip heral
operations
2.2.1 Microprocessor-Initiated Operations
x They represent the basic communication between the microprocess or with
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¾ Memory Read a It indicates reading data or instruction from the
memory
¾ Memory Write a It indicates writing data or instruction to the memory
¾ I/O Read a It indicates reading data from the input device
¾ I/O Write a It indicates writing result to the output device
x To perform any of these operation the microprocessor executes t he following
step
¾ Step 1: Identify location of memory register or I/O device – This is
achieved with the help of the address bus which identifies the location.
The 8085 microprocessor has 16 bit unidirectional address bus t o
perform this step.
¾ Step 2: Transfer data or instruction – This can be achieved with the
help of the data bus. The 8085 microprocessor has 8 bit data bu s to
carry information from/to memory or I/O device.
¾ Step 3: Provide timing and control signal – T his can be achieved
with the help of the control bus. The 8085 microprocessor provi des four
control signals depending on the nature of operation to be perf ormed.

Figure 2.1 – Microprocessor and bus structure


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2.2.2 Internal Operations
x The internal architecture of the microprocessor unit (MPU) is s olely
responsible for the various internal operations.
x The 8085 MPU has ALU, internal bus, general-registers, accumula tors,
program counter and stack pointer to serve the purpose.
x The operation include storing data in registers, performing ari thmetic and
logical calculations, checking conditions, executing the instru ctions in
sequence and using stack for temporarily processing the data. ACCUMULATOR (A REGISTER) FLAG REGISTER D7 D6 D5 D4 D3 D2 D1 D0 S = AC P C<
B C D E H L STACK POI1TER (SP) PROGRAM COU1TER (PC) ADDRESS BUS DATA BUS
Figure 2.2 – Microprocessor internal structure
x For example, consider the following assembly program 2000 0E MVI C, 65H 2001 65 2002 0C I1R C 2003 79 MOV A, C 2004 76 HLT x The first instruction is written at address 2000H and this valu e is loaded in
program counter and execution begins.
x The processor decodes and executes the instruction at 2000H, it increments
the value in program counter 2001H and fetches the next code an d concludes
by interpreting that value 65H be written in C register.
x Then program counter is incremented to next address which is 20 02H and the
instructions increments the value in C register.
x The next address in program counter will be 2003H which is deco ded as
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x The last address in program counter is 2004H which indicates en d od
execution
x So for basic internal operations the various registers of the m icroprocessor
are used.
2.2.3 Peripheral Operations
x The peripherals or I/O devices are the external devices that ca rry out this
operation and hence this category is commonly called as externa lly-initiated
operation.
x Certain individual pins of the m icroprocessor perform this type of operation
x They include reset, interrupt, ready and hold pin.
2.3 Memory
x The integral and important component of the microcomputer is th e storage
device i.e. the memory.
x The microprocessor reads data and programs (here instructions) from the
memory and stores results to the memory.
x The microcomputer system has two types of memory – Read Only Memory
and Read/Write Memory
x The Read Only Memory is non-volatile that stores system level p rograms
available to system all time.
x The Read/Write memory holds program and data which can be read and
written by the programmer and are volatile in nature.
x To read/write information from any kind of memory the microproc essor
performs the following steps
¾ Select the right memory chip
¾ Identify the exact memory location in the selected chip
¾ Access the data available at the identified location
2.3.1 Flip-Flop or Latch as Storage Element
x Memory is defined as a circuit that stores voltage level or ele ctric charge
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x So a basic feature of memory that stores the binary bits is the flip-flop or
latch.
x D latch or flip-flop is the ideal choice for a memory element.
x The latch includes one input line, one output line, and an enab le input that
allows the latch to be triggered.
x For securing and controlling the data in and out of latch, we u se tristate
buffers at input and output line.

Figure 2.3 – Basic D Latch with Tristate Buffers
x The input buffer in controlled by the active low control signal write ( ܴܹതതതതതሻ
and the output buffer is controlled by the active low control s ignal read ( ܦܴതതതതሻ
x This latch is called as a memory cell capable of storing a bina ry bit or digit.
x In order to create a memory register, several such latches need s to be
combined together.
x For example four latches have been connected to create a memory register
identified as 1 x 4 where 1 represents count of memory register and 4
represents the number of bits the individual register can hold.

Figure 2.4 – 1 [ 4 memory organi]ation
y So a simplified block diagram to represent the above constructi on.
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25Chapter 2: Microprocessor Architecture and Microcomputer System s
y The Enable signal (E1) enables the register and the write or re ad operation
can be performed in the register by enabling the input or outpu t buffer
respectively with the control signal.

Figure 2.5 – 1 [ 4 memory register block diagram
y We can now expand the diagram by adding several memory register s to create
a memory chip.
y Using interfacing logic with help of decoder, we can select ind ividual
registers and perform write or read operation by enabling the i nput or output
buffer respectively.
y Let’s construct as 4 x 4 memory i.e. 4 registers each capable of storing a 4 bit
word.
y When count of registers increases then the enable signal is rep laced by
address lines for register selection.
y Two address line A 1-A0 are connected to decoder for selecting the register.
y Four combinations (00, 01, 10 and 11) will select the register (0, 1, 2 and 3).

Figure 2.6 – 4 [ 4 memory register block diagram
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y We shall further expand with eight registers on one chip each c apable of
storing 8 bits/1 byte of data.
y For this we will require three address lines A 2 – A0 which provides eig ht
combinations (000, 001, 010, 011, 100, 101, 110, 111) for regis ter select.

Figure 2.7 – 8 [ 8 memory register block diagram
y And if we have 16 registers, we need four address lines and thi s calculation
goes on. No. of address lines Si]e of memory 1 2 2 4 3 8 4 16 5 32 6 64 7 128 8 256 9 512 10 1024 ≈ 1K 11 2048 ≈ 2K 12 4096 ≈ 4K 13 8192 ≈ 8K 14 16384 ≈ 16K 15 32768 ≈ 32K 16 65536 ≈ 64K Table 2.1 – Memory si]e and address line relationship
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y We can also build memory on several chips.
y For example the above 8x8 memory organization can also be arran ged on two
chips with each chip having 4 registers each.
y Same three address lines will be used but A 1 – A0 will be used to select the
individual registers and A 2 will be used to select the memory chip.

Figure 2.8 – 8 [ 8 memory register with chip select
y As the number of registers increase we use a chip select ( ܵܥതതതതሻ logic which is
active low signal and acts as master enable pin to decide to pe rform read or
write operation.
y So now we construct a typical re ad/write and read only memory c hip.

Figure 2. – R/W and ROM model
y The difference between the models is concerned with address dec oding and
most notable difference is that the ROM does not include ܴܹതതതതത signal.
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2.3.2 Memory Map and Addresses
x The 8085 microprocessor has 16 address wires or lines and there fore can
identify a maximum of 216 655536 registers.
x The entire memory address range can be represented as
Table 2.2 – Memory map A1
5 A1
4 A1
3 A1
2 A1
1 A1
0 A A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x The above table is called the memory map which is the pictorial
representation of the address range.
x The address range is 0000H to FFFFH.
x We shall now see a memory organization of 256 registers with 8 data lines
i.e. this memory called as 256 x 8 memory organization.
x 256 28. So 8 address lines (A 7—A0) are used for selecting memory register
and remaining 8 address lines (A 15—A8) are used for chip select ( ܵܥതതതതሻ logic
and two control signals Write ( ܴܹതതതതത) and Read ( ܦܴതതതത) for data storage and
retrieval respectively.
x For register select the address line are connected to internal decoder and for
chip select the address line are connected to 1A1D gate via inv ertors.
x So when the 1A1D gate output is low the memory chip is selected .

Figure 2.10 – 256 [ 8 memory model
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x The memory address range for 256 x 8 memory is represented as A1
5 A1
4 A1
3 A1
2 A1
1 A1
0 A A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Chip Select Register Select Table 2.3 – Memory map
x The address range is 0000H to 00FFH.
x We shall now see a memory organization of 8192 registers with 8 data lines
i.e. this is referred as a memory size of 8192 x 8.
x 8192 213. So 8 address lines (A 12—A0) are used for selecting memory
register and remaining 3 address lines (A 15—A13) are used for chip select
(ܵܥതതതതሻ l o g i c a n d t w o c o n t r o l s i g n a l s W r i t e ( ܴܹതതതതത) and Read ( ܦܴതതതത) for data
storage and retrieval respectivel y with same logic applied for interfacing.

Figure 2.11 – 812 [ 8 memory model

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30MICROPROCESSOR ARCHITECTURE
x The memory address range for 8192 x 8 memory is represented as A1
5 A1
4 A1
3 A1
2 A1
1 A1
0 A A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Chip Select Register Select Table 2.4 – Memory map
x The address range is 0000H to 1FFFH.
x We can construct any memory based on above logic and calculate the address
range on the memory chip.
2.3.3 Word Si]e of Memory
x Memory device come in different word size measured in bytes and memory
chip comes in number of bits it stores.
x For example, a memory chip of size 512 x 4 means 512 registers individually
which stores 4 bits and total memory chip size calculated as 51 2 x 4 2048
bits.
2.3.4 Instruction Fetch from Memory
x The purpose of memory is to store data and instructions, so MPU i s s u e s
command to access it.
x This is done by sending the address of the specific memory regi ster via the
address bus and enable the data flow depending on the control s ignal issued.
x For example the memory address 2000H contains the instruction M OV E, A
Memory Address Hex Code Binary Code Mnemonic
2000 5F 0101 1111 MOV E, A
x The sequence of steps are
¾ The instruction is available at address 2000H and this value in loaded
in program counter.
¾ 1ow the control unit issues the active low memory read ( ܴܯܧܯതതതതതതതതതሻ
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¾ The code 5F(0101 1111) for the instruction MOV E, A available a t
location 200H is now placed in data bus
¾ The code is now loaded in instruction register and is decoded w here the
content of accumulator is copied into E register.

Figure 2.12 – Instruction Fetch Operation
2.3.5 Classification of Memory
x Memory is integral part of microcomputer system and are primari ly classified
into primary and secondary memory which further have several su b types.

x Main or primary memory contains data and instructions which com puter is
currently using.
¾ The Read/Write or Random Access Memory (RAM) is volatile
memory which stores data, instructions and immediate output.
ƒ Static RAM is built of flip-flops and holds data without extern al
refresh and is expensive but high speed memory chip.
ƒ Dynamic RAM is built of MOS transistor gates which must be
refreshed many times with low power consumption, high density
and cheaper than static RAM.
MemoryMainRead/WriteStaticDynamicRead OnlyMasked
ROMPROMEPROMEEPROMFlash
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x The Read Only Memory (ROM) is non-volatile memory which stores system
level programs that PC want at all times.
ƒ Masked ROM are hard-wired and bit masking is done by metallizat ion
process usually by the manufacturers.
ƒ Programmable ROM (PROM) is diode-based and programmed using
special devices that burn the fuses for storage of the appropri ate bit
pattern.
ƒ Erasable PROM (EPROM) can be programmed as it stores bits by
charging and erasing the floating gate. Erasing is done using U V rays
and hence entire memory content will be erased and can be
reprogrammed again.
ƒ Electrically Erasable PROM (EEPROM) – S i m i l a r t o E P R O M w i t h
difference that erasing is done under software control at regis ter level
instead of entire chip.
ƒ Flash Memory are advanced level with erasing done at sector lev el or
entirely and can be reprogrammed million times.
x Secondary memory or storage memory store information and result s after
execution and are non-volatile and stored for future reference.
Microprocessor cannot execute programs from here and hence have to be
loaded in main memory for execution.
¾ The magnetic tapes are serial access device with high capacity but slow
access.
¾ The disks are semi-random devices made of metal and plastic sca nned
by a laser beam.
2.4 I/O DEVICES
y Input/ Output (I/O) devices or peripherals help the microproces sor
communicate with the external world.
y Through input devices such as keyboard the system accepts input and th e
results are displayed via the output devices such as display an d printers
y Communication with the I/O device can be established using eith er an 8-bit
address (Peripheral- Mapped I/ O) or 16-bit address (Memory-Mapp ed I/O).
y The steps of communication between microprocessor and periphera ls are
¾ Identify the I/O device by placing the address on the address b us.
¾ Depending on operation to be performed the MPU issues read ( ܴܱܫതതതതതሻ
and write ( ܹܱܫതതതതതതሻ control signal on the control bus.
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2.4.1 Peripheral-Mapped I/O
y It is known as I/O Mapped I/O.
y Eight address lines are used for I/O interface recognition.
y 28 256. Thus, 256 input and output devices with a range of 00H to FFH can
be identified.
y To access or read from input device active low I/O Read control signal ( ܴܱܫതതതതതሻ
is generated and to access or write to output device active low I / O Write
control signal ( ܹܱܫതതതതതതሻ is generated by the MPU.
2.4.2 Memory-Mapped I/O
x The I/O devices are assumed as memory registers and therefore 1 6 address
lines are used for identification.
x The MPU uses the control signal active low Memory Read ( ܴܯܧܯതതതതതതതതതሻ and
active low Memory Write ( ܹܯܧܯതതതതതതതതതതሻ to access the memory.
2.5 Microcomputer System Illustration
y We now develop a microcomputer system based on previous study.
y The system includes 8085 MPU, memory (EEPROM and R/W Memory),
input and output devices and all interconnected using the vario us system bus.
y The MPU communicates with only device at a time by issuing the
corresponding control signal.
y Address of memory location is identified by A 15 –A0 a n d I / O d e v i c e a r e
identified by A 7- A 0 using the address bus
y Data bus D 7-D0 is common for all and bidirectional

Figure 2.13 – Microcomputer System Illustration
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2.6 Logic Devices
x Several types of interfacing devices are necessary to interface t h e
microprocessor with memory and peripherals to establish the com munication
using the buses.
2.6.1 Tri-State Device
x 1ormal logic devices have two states – Logic 0 and Logic 1
x As name indicate these devices have a three output states – Logic 0, Logic 1
and high impedance state
x This state is to effectively remove the device influence from r est of the circuit.
x Tristate devices have enable line to confirm whether device wor ks in normal
state or high impedance state
x Tristate buffer and tristate inve rtor are commonly used interfa cing devices.
x When enable is high these device act as normal device and when enable line
is low, the device enters into high impedance state.

Figure 2.14 – Tristate Devices
2.6.2 Decoder
y Decoder is a logic circuit that converts binary information fro m n input to 2n
output.
y So in high performance memory system decoders can minimize the effect of
memory selection.
y Each combination of input lines helps to select a single unique m e m o r y
register.
y Example 2:4 Decoder, 3:8 Decoder and so on.
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Figure 2.15 – Decoder
2.6.3 Encoder
x Encoder is opposite of decoder whe re it provides output for eac h input
signal
x Single input line produces a corresponding output, but however if two or
more input lines gets activate d then appropriate output code ca nnot be
generated
x They are commonly used device for interfacing with keyboards.

Figure 2.16 – Encoder
2.6.4 D Flip-Flop
x It is most essential device while interfacing the output device s
x The MPU holds data in the data bus only for few microseconds an d it is very
important to latch the data before it is lost
x So D latch or flip-flop serves this purpose.

Figure 2.17 – D FF
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2.7 Application: MCTS
y The application discussed in the last chapter is now expanded w ith interfacing
devices included.
y Decoder is required to interface each device
y The input device in this case temperature sensor are interfaced using buffer
y The output devices in this case fan, heater and LCD are interfa ced using the
latch

Figure 2.18 – MCTS Application
2.8 Summary
y The microprocessor performs basic four operations such as Memor y Read
(ܴܯܧܯሻതതതതതതതതതത, Memory Write ( ܹܯܧܯሻതതതതതതതതതതത, I/O Read ( ܴܱܫሻതതതതതതത, I/O Write ( ܹܱܫሻതതതതതതതത.
y The address bus, data bus and control bus govern the entire com munication
between MPU, memory and peripherals
y The architecture of 8085 is robust to handle different kinds of operation.
y Memory is integral part of MPU and different types of memories help in
execution of different activities of the microprocessor all ide ntified by 16 bit
address.
y I/O devices are interfaced either by 8 bit address or 16 bit ad dress.
y To interconnect peripherals and M PU several interfacing devices are used to
ease the operation
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37Chapter 2: Microprocessor Architecture and Microcomputer System s
2. List of References
x Ramesh Gaonkar, “Microprocessor Architecture, Programming and
Applications with the 8085”, Fifth Edition, Penram International Publishing
(I) Private Limited
x B. Ram, “Fundamentals of Microproc essor and Microcomputers”. Sixth
Revised and Enlarged Edition, Dhanpa t Rai Publications (P) Limi ted
x https://www.tutorialsmate.com/ 2020/04/types-of-computer-memory. html
2.10 Unit End E[ercise
1. Explain the operation performed by the 8085 microprocessor"
2. Explain the role of 8085 system bus is communication of MPU wit h
peripherals.
3. What is memory" Draw and explain the memory organization of 16x 8
registers on 1 chip and 2 chips with 4 address lines.
4. Illustrate the memory map and address range of the chip with 40 96 bytes and
explain how the range can be changed by modifying the hardware of the chip
select line
5. Explain the following interfacing devices: (A) Tristate device (B) Buffer (C)
D-Flip flop

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UNIT 1
3
8085 MICROPROCESSOR ARCHITECTURE
AND MEMORY INTERFACING
Unit Structure
3.0 Objectives
3.1 Introduction
3.2 8085 Microprocessor Unit
3 . 2 . 1 8 0 8 5 M i c r o p r o c e s s o r
3 . 2 . 2 M i c r o p r o c e s s o r c o m m u n i c a t i o n a n d b u s s y s t e m
3.2.3 Demultiplexing the address-data bus
3.2.4 Generating Control Signals
3 . 2 . 5 T h e 8 0 8 5 M i c r o p r o c e s s o r A r c h i t e c t u r e
3.3 8085 based Microcomputer Illustration
3 . 3 . 1 T h e 8 0 8 5 M a c h i n e C y c l e
3 . 3 . 2 O p c o d e F e t c h C y c l e
3.3.3 Memory Read Machine Cycle
3.3.4 Memory Write Machine Cycle
3.3.5 How to Recognize Machine Cycle
3.4 Memory Interfacing
3.4.1 Memory structure and its requirements
3.4.2 Basic concepts in memory interfacing
3.4.3 Address Decoding and Memory Address
3.4.3.1 Read Only Memory Chip
3 . 4 . 3 . 2 R e a d / W r i t e M e m o r y C h i p
3.5 Interfacing 8155 Memory Segment
3.6 Designing Memory for MCTS Project
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39Chapter 3: 8085 Microprocessor Architecture and Memory Interfac ing
3.7 Testing and Troubleshooting Memory Interfacing Circuit
3.7.1 Testing
3 . 7 . 2 T r o u b l e s h o o t i n g
3 . 7 . 3 D i a g n o s t i c R o u t i n e
3.8 8085-Based Single-Board microcomputer
3.9 Summary
3.10 List of references
3.11 Unit End Exercise
3.0 Objectives
After going through this chap ter, you will be able to
x Understand the purpose of each pin
x Know the role of system bus in decoding and executing an instru ction
x Know the different techniques available in memory interfacing
x Understand the difference between absolute and partial decoding
x 1eed for testing and troubleshooting memory interface circuit.
3.0 Introduction
x The 8085 microprocessor is enhan ced version of its predecessor 8080A.
x Introduced in the year 1976, the 8085 is the predominantly and widely
accepted 8 bit microprocessor.
x The instruction set of 8085 is upward compatible with additiona l instructions.
3.1 8085 Microprocessor Unit
x The 8085 is 8-bit general purpose microprocessor packaged as du al inline
package (DIP) with 40 pins.
x It works on single 5V power supply and operates on 3MHz clock frequency.
x It has 16 address lines with which it can address 64K memory an d 8 data
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3.1.1 8085 MICROPROCESSOR
x The Pin diagram of 8085 microprocessor is categorized into six groups

Figure 3.1 – Pin Configuration
x Address bus
o There are 16 address lines which are unidirectional
o The first eight pins A 15 - A 8 carry the high order address i.e. the most
significant bits and the remaining eight pins A 7 - A 0 are combined with
data bus which holds the low order address i.e. the least signi ficant bits
and data.
x Multiple[ed Address-Data bus
o There are eight pins that serve dual purpose – It holds low order address
and data and are identified as AD 7 – AD 0.
o When they hold the address the lines are unidirectional and whe n the
lines hold data they are bidirectional
o During instruction execution, initially these pins hold address which is
latched and then same pins hold data during the latter part of the
execution.
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x Control and status signals
o Address Latch Enable (ALE) is output signal which determines th e
multiplexed bus contains address or data. ALE = 1 →AD 7 – AD 0 holds
address and ALE = 0 → AD 7 – AD 0 holds data.
o Read ( ܦܴതതതതሻ is active low output signal to read from memory location or
peripherals.
o Write ( ܴܹതതതതതሻ is active low output signal to write to memory location or
peripherals.
o Input-Output/Memory (IO/ ܯഥሻ is output status signal to help the
microprocessor differentiate between peripheral and memory rela ted
operation. IO/ ܯഥ = 1 → perip heral operation and IO/ ܯഥ = 0 → memory
operation.
o Status signal (S1 & S0) are rarely used output status signal fo r status of
operation of microprocessor.
x Power supply and frequency signals
o Power Supply (V cc) is 5V
o Ground (V ss) – 0V
o Clock Input (; 1 and ; 2) are input pins connected to crystal to make the
system operate at 3MHz and so crystal should have 6MHz.
o Clock Output (CLK OUT) is output signal used as system clock to
trigger other devices.
x E[ternally initiated signals
o Interrupt Request (I1TR) is active high input signal for genera l purpose
interrupt.
o Interrupt Acknowledge ( ܣܶܰܫതതതതതതത) is active low output signal for response
to the I1TR signal.
o Restart Interrupts (RST 7.5, RST 6.5 and RST 5.5) are active hi gh input
maskable interrupts with RST 7.5 is edge triggered and other tw o are
level triggered.
o Trap (TRAP) interrupt is active high input edge and level trigg ered and
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o Hold (HOLD) is active high input signal to allow Direct Memory
Access (DMA) between peripherals and memory.
o Hold Acknowledge (HLDA) is active high output response to HOLD
signal.
o Ready (READ<) is active high input control signal to delay the read or
write operation as peripherals are slow devices compared to
microprocessor
o Reset Input ( ܰܫܶܧܵܧܴതതതതതതതതതതതതതሻ is active low signal to reset the
microprocessor by setting program counter address to 0000H and buses
in tristate mode.
o Reset Output (RESET OUT) is active high signal by the
microprocessor to reset other devices.
x Serial I/O ports
o Serial Input Data (SID) is acti ve high input signal for serial
transmission.
o Serial Output Data (SOD) is active high output signal for seria l
reception.
3.1.2 Microprocessor Communication and Bus System
x The communication process is four-fold.
x First step involves the microprocessor placing the 16-bit addre ss on the
program counter.
x 1ext the active low read control signal ( ܦܴതതതത) on the control bus
x The data in the memory location identified by the address in no w on placed
on the data bus.
x The data bus carries it to instruction decoder where the action is taken
according to the instruction.
x The diagram represents the execution of the instruction MOV C, A stored in
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Figure 3.2 – Communication flow of instruction e[ecution
3.1.3 Demultiple[ing the Address-Data Bus
x In 8085, the high order address lines A 15 - A 8 are directly available.
x The low order address lines ar e multiplexed with data bus as AD 7– AD 0.
x So it necessary to demultiplex (separate) the address and data.

Figure 3.3 – Latching the multiple[ed bus
x Execution of any instruction (opcode ) requires four clock perio d.
x The high order address is available for three clock period and low order is
available for only one clock period and hence will be lost
x So we save the address in a latch which is enabled by ALE pin.
x When ALE is high, the latch is enabled and the bus contains add ress which
is stored in latch and when ALE is low the latch is disabled an d the bus now
contains data which is directly used.


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44MICROPROCESSOR ARCHITECTURE
3.1.4 Generating Control Signals
x The control bus is responsible for carrying the control signal which tells the
operation the microprocessor is to perfom.
x Three pins read ( ܦܴതതതതሻ, write ( ܴܹതതതതതሻ and Input-Output/Memory (IO/ ܯഥሻ are
combined to generate four control signals.
x The signals can be generated using negative 1A1D gates or a 3:8 decoder.
Using negative NAND gate Using 3:8 Decoder Figure 3.4 – Generating the control signal
3.1.5 The 8085 Microprocessor Architecture
x The architecture is divide d into five functional groups.

Figure 3.5 – 8085 Architectural Block Diagram

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x Arithmetic and Logical Group
o It includes the Arithmetic-Logic Unit which performs the arithm etic
operation like addition, subtraction, increment and decrement a nd
logical operation like A1D, OR, ;OR, complement, compare and
rotate.
o An 8-bit general purpose register called accumulator or ‘A’ re g i s t e r
which holds one of the operand and result of the most of the op eration.
o An 8-bit temporary register not available for programmer but us ed by
microprocessor for certain operation
o A 8 bit flag register (made up of flip-flops) which defines fiv e flags
which are set (value 1) or reset (value 0) depending on the result of
the arithmetic and logical operation
o The various flag flip-flops are are Sign (S), =ero (=), Auxilia ry Carry
(AC), Parity (P) and Carry (C<) flag.

Figure 3.6 – 8085 Flag Register Format
x Register Group
o A pair of temporary register W and = not available to the progr ammer
but used by the microprocessor during the stack operations.
o Six general purpose 8-bit register B, C, D, E, H and L to store data.
o They are combined to form register pairs BC, DE and HL to store 16-
bit data.
o A 16-bit program counter (PC) to hold the address of the instru ction to
be executed and which keeps incrementing to fetch the next inst ruction
till the end of program.
o A 16-bit stack pointer register used as pointer to stack locati on where
data is stored temporarily.

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46MICROPROCESSOR ARCHITECTURE
x Interrupt Control Group
o Various interrupt pins discussed earlier like TRAP, RST 7.5, RS T 6.5
and RST 5.5, are handled by executing the Interrupt Service Rou tine
(ISR) at the corresponding vector address to decide the action to be
taken when the interrupt occurs.
o For the interrupt I1TR, it generates ܣܶܰܫതതതതതതത signal to acknowledge and
send opcode of CALL instruction to transfer control to that add ress
mentioned by the interrupting device.
x Instruction Register, Decoder and Control Unit Group
o The Instruction Register (IR) is 8bit register that stores opco de of the
current instruction being executed and used only by the micropr ocessor
and not the programmer.
o The Instruction Decoder accepts opcode from IR then decodes it and
sends information to control logic to perform operation specifi ed by the
instruction.
o The timing-control unit generates various signals to sequence a nd
synchronize the microprocessor operation.
x Serial I/O Group
o The 8085 is a parallel device but using the pins SID and SOD it can
support serial transmission and reception and also instruction RIM and
SIM help in performing serial transfer.
3.2 8085 Based Microcomputer Illustration
x The 8085 microprocessor executes the instruction in terms of in struction
cycle, machine cycle and T-states
x The time taken for the complete execution of single instruction is the
instruction cycle.
x The time taken for the complete execution of one operation such as accessing
memory or peripheral is the machine cycle.
x One sub division of operation performed in synchronization with s y s t e m
clock is called the T-state.
x The 8085 one instruction cycle can have one to six machine cycl e and each
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3.3.1 The 8085 Machine Cycle
x There are 74 instructions in 8085 microprocessor and instructio n is made of
opcode and operand.
x Some instructions are one byte and some multi-byte.
x Hence different machine cycles such as opcode fetch, memory rea d/write,
I/O read/write are required for the decoding and execution.
3.3.2 Opcode Fetch Cycle
x All 8085 instruction must have opcode as compulsory part and op erand is
optional.
x So the first machine cycle of any instruction is opcode fetch c ycle which has
four T-states.
x It uses the first three states T1 —T3, to fetch the code and T4 to decode and
execute the opcode.
x The high order address A 15 - A 8 is available for three T-states.
x The multiplexed bus AD 7– AD 0 hold low order address during T1 which is
indicated by ALE signal going high and between T2- T3 holds the data
indicated as ALE goes low.
x Opcode fetch is a memory operation and indicated by status sign als IO/ ܯഥ, S1
and S 0 011.
x When opcode (data) is placed in the data bus the read signal ( ܦܴതതതതሻgoes low
to enable the operation.
3.3.3 Memory Read Machine Cycle
x The memory read machine cycle requires three T-states to perfor m the
operation.
x The high order address and multiplexed address data bus logic r emains same
as opcode fetch cycle.is available for three T-states.
x Memory read operation is indicated by status signals IO/ ܯഥ, S1 and S 0 010.
W h e n d a t a i s p l a c e d i n t h e d a t a b u s from memory location the r ead signal
(ܦܴതതതതሻgoes low to enable the operation.

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3.3.4 Memory Write Machine Cycle
x The memory read machine cycle requires three T-states to perfor m the
operation.
x The high order address and multiplexed address data bus logic r emains same
as opcode fetch cycle.is available for three T-states.
x Memory write operation is indicated by status signals IO/ ܯഥ, S1 and S 0 001.
x When data is placed in the memory location from the data bus no w instead
of read, the write signal ( ܴܹതതതതതሻ goes low to enable the operation
Opcode Fetch Cycle Memory Read Cycle Memory Write Cycle Figure 3.7 – 8085 Machine Cycle
3.3.5 How To Recogni]e Machine Cycle
x The first illustration is execution of the instruction MVI B, 4 3H stored in
address 2000H.
x It is a two byte instruction and it requires two machine cycle to execute the
instruction.
x The first machine cycle is opcode fetch which requires four T-s tates and
second machine cycle is memory read which requires three T-stat es and so a
total of seven T-states. Memory Address Mnemonic He[ / Machine Code 2000 MVI B, 43H 06 (0000 0110) 2001 43 (0100 0011)
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x In the first machine cycle the microprocessor decodes the opcod e as seen in
the opcode fetch machine cycle and in the second machine cycle the memory
places the data byte on the data bus which is then stored in re gister B at the
end of T 3.
x The execution time of the i nstruction is calculated as
o Let us assume the Clock frequency f 2 MHz
o T-state cloc k period (1/f) 0.5 Ps
o Execution time for 1st Machine Cycle
(Opcode Fetch) 4T x 0.5 2 Ps
o Execution time for 2nd Machine Cycle
(Memory Read) 3T x 0.5 1.5 Ps
o Total Execution time for Instruction: 2 Ps  1.5 Ps 3.5 Ps

Figure 3.8 – Machine Cycles for the instruction MVI B, 43H
x Consider another illustration of executing the instruction STA 8000H stored
in memory address 2050H.
x It is a three byte instruction but it requires four machine cyc le to execute the
instruction.
x There is no direct relationship betw een the number of bytes of instruction
and the number of machine cycles required to decode that instruction.
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x The first machine cycle is opcode fetch which requires four T-s tates and
second and the third machine cycle is memory read with three T- states each
followed by final cycle of memory write with three T-states mak ing it a total
of thirteen T-states.
x In the opcode fetch cycle, the microprocessor places the addres s 2050H in
address bus and opcode 32H in data bus.
x In the first memory read cycle the microprocessor reads the add ress 2051H
and the data bus reads the low order byte 00H.
x In the second memory read machine cycle the microprocessor read s the
address 2052H and the data bus rea ds the high order byte 80H.
x In the last cycle the address 8000H is placed in the address bu s and the byte
available in the accumulator is stored in this location via the data bus.
x The execution time of the i nstruction is calculated as
o Let us assume the Clock frequency f 2 MHz
o T-state cloc k period (1/f) 0.5 Ps
o Execution time for 1st Machine Cycle
(Opcode Fetch) 4T x 0.5 2 Ps
o Execution time for 2nd Machine Cycle
(Memory Read) 3T x 0.5 1.5 Ps
o Execution time for 3rd Machine Cycle
(Memory Read) 3T x 0.5 1.5 Ps
o Execution time for 4th Machine Cycle
(Memory Write) 3T x 0.5 1.5 Ps
o Total Execution time for Instruction:
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51Chapter 3: 8085 Microprocessor Architecture and Memory Interfac ing

Figure 3. – Machine Cycles for the instruction STA 8000H
3.4 Memory Interfacing
x Memory is an important component of the microprocessor based sy stem
where we store data, program and results.
x So the memory must be properly interfaced so it can be easily a nd frequently
accessed to read data and instruc tions and write results to it.
3.4.1 Memory Structure and its Requirements
x The microprocessor based system possess Read Only memory chip w ith 4096
registers and R/W memory chip with 2048 registers and each regi ster capable
of storing 8 bits.
Read Only Memory Chip
(406 [ 8) R/W Memory Chip (2048 [ 8) Figure 3.10 – Memory Chip

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3.4.2 Basic Concepts in Memory Interfacing
x The basic idea of memory interfacing involves foremost selectin g the
memory chip, followed by the identifying individual register an d enabling
the buffer for the right operation.
x The memory read and write cycle explained earlier illustrates t he interfacing
concept.
3.4.3 Address Decoding and Memory Address
x Address decoding is the process of identifying the memory chip and register
for a given address.
x A unique pulse identifies the address and this pulse can be gen erated using
1A1D gate and 3:8 Decoder.
x The output of 1A1D gate selects the chip when address A 15- A 12 will be
high.
x The same result can be obtained 3:8 decoder which can decode 8 devices
based on the address bits A 14- A 12. Using NAND Gate Using Decoder Figure 3.11 – Interfacing Techniques
3.4.3.1 Read Only Memory Chip
x A typical EPROM memory with 4096 registers is used which is ide ntified by
12 address lines A 11—A0, one chip select signal and only one control signal
ܦܴതതതത to activate output buffer.
x The address lines A 11—A0 are connected to memory chip to select register.
x The address lines A 14—A12 are connected as inputs to 3:8 decoder which
when asserted low selects the chip ( ܧܥതതതത) and A 15 is connected to enable pin of
the decoder.
x So the value A 15—A12 0000 enables the decoder to assert output through
O0.
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x The control signal ܴܯܧܯതതതതതതതതത i s g e n e r a t e d b y O R i n g I O / ܯഥ and ܦܴതതതത w h i c h
enables the output buffer ܧܱതതതത.

Figure 3.12 – Interfacing 406 [ 8 EPROM Memory
x The address range for the above memory would be A15 A14 A13 A12 A11 A10 A A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Chip Select Register Select Table 3.1 - Memory map for 406 [ 8 EPROM
x The range is 0000H - 0FFFH.
3.4.3.2 Read/ Write Memory Chip
x A typical R/W memory with 2048 registers is used which is ident ified by 11
address lines A 10—A0, one chip select signal and control signals
x The address lines A 10—A0 are connected to memory chip to select register.
x The address lines A 13—A11 are connected as inputs to 3:8 decoder which
when asserted low selects the chip ( ܧܥതതതത) and remaining address lines A 15 and
A14 along with IO/ ܯഥ is connected to enable pin of the decoder
x So the value A 15—A11 10001 enables the decoder to assert output through
O1.
x The control lines ܦܴതതതത and ܴܹതതതതത are directly connected to memory chip to
enable output and input buffer respectively and the signals ܴܯܧܯതതതതതതതതത and
ܹܯܧܯതതതതതതതതതത are not generated.
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Figure 3.13 – Interfacing 2048 [ 8 R/W Memory
x The address range for the above memory would be A15 A14 A13 A12 A11 A10 A A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Chip Select Register Select Table 3.2 - Memory map for 2048 [ 8 R/W Memory
x The address range is 8800H - 8FFFH.
x Both the memory chips used all address lines for decoding and t his is
known as absolute decoding .
3.5 Interfacing 8155 Memory Segment
x The 8155 is multipurpose programmable device interfacing the pe ripherals
the 8085 microprocessor containing memory (256 bytes R/W memory ), I/O
ports (three ports 8-bit each) and timer.
x The 256 x 8 memory is identified with 8 address lines A 7-A0 a n d t h e
remaining address lines A 15-A11 a r e c o n n e c t e d t o d e c o d e r w i t h A 15-A14
connected to enable pin and A 13-A11 connected to input of the decoder and
output O 4 of the decoder is asser ted low to enable the chip. So A 15-A11
00100 enables the decoder.
x The control signals IO/ ܯഥ, ܦܴതതതത and ܴܹതതതതത are directly connected to the memory
chip to enable the buffer.
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55Chapter 3: 8085 Microprocessor Architecture and Memory Interfac ing
8155 Memory Section Interfacing 8155 Memory Figure 3.14 – 8155 Memory and SDK-85
x The address lines A 10-A8 are not connected and considered as don’t care
lines.
x This interfacing technique where all address lines are not used for decoding
is called as partial decoding and advantageous as cost saving technique.
x The address range for the above memory is called foldback or mi rror
memory. A15 A14 A13 A12 A11 A10 A A8 A7 A6 A5 A4 A3 A2 A1 A0 Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 20FFH 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 2100H 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 21FFH 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 2200H 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 22FFH 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 2300H 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 23FFH 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 2400H 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 24FFH 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 2500H 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 25FFH 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 2600H 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 26FFH 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 2700H 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 27FFH Chip Select Don’t Care Register Select Table 3.3 - Memory map for 256 [ 8 R/W Memory
x The primary address range is 2000H -20FFH and foldback memory r ange is
2100H – 27FFH.

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3.6 Designing Memory for MCTS Project
x The interfacing circuit for microprocessor controlled temperatu re system
MCTS studied in the earlier chapter includes 4K x 8 EPROM and 2 K x 8
R/W Memory and 3:8 Decoder for interfacing.

Figure 3.15 – MCTS Project Memory Interfacing
x The EPROM memory with 4K memory is identified by 12 address lin es
A11—A0 and remaining address lines A 15—A12 0000 with O 0 of decoder
asserted low to enable the chip and ܦܴതതതത directly connected to enable output
buffer. A15 A14 A13 A12 A11 A10 A A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Chip Select Register Select Table 3.4 - Memory map for 4K EPROM
x The range is 0000H - 0FFFH
x The R/W memory with 2K memory is identified by 11 address lines A10—
A0 and remaining address lines A 15—A12 0010 with O 2 of decoder asserted
low to enable the chip and ܦܴതതതത directly connected to enable output buffer and
ܴܹതതതതത directly connected to enable the input buffer.
x The address line A 11 is not connected resulting in foldback memory.

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57Chapter 3: 8085 Microprocessor Architecture and Memory Interfac ingA15 A14 A13 A12 A11 A10 A A8 A7 A6 A5 A4 A3 A2 A1 A0 Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 27FFH 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2800H 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 2FFFH Chip Select Don’t Care Register Select x The primary address range is 2000H -27FFH and foldback memory r ange is
2800H – 2FFFH.
3.7 Testing and Troubleshootin g Memory Interfacing Circuit
x Memory is integral part of microcomputer system as it holds dat a and
instructions
x Hence testing and troubleshooting of memory is fairly important to check the
integrity of the contents.
3.7.1 Testing
x Testing is simply done by randomly choosing a memory location a nd writing
the data byte at that location with help of keyboard and then r eading the
content of the same memory location and displaying the result i n display.
x If the content matches then memory is available and we can repe at this test
at different memory locations.
x When we cannot load a byte then we need to perform troubleshoot ing.
3.7.2 Troubleshooting
x The best way to perform troubleshooting is visual inspection.
x We check wires, pin connections which is easy but logic level o f buses
checking is difficult as it is dynamic.
x Signal injection is useful technique where signal is injected a t input and check
output as per expected outcome
x To perform signal injection we write diagnostic routine.
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3.7.3 Diagnostic Routine
x Diagnostic routine involves writing continuous loop.
l o o p : M V I A , A A H
S T A 2 0 0 0 H
JMP loop
x The infinite loop loads value AAH in accumulator and then store s the value
in the memory location 2000H and this process is repeated infin itely.
x We can diagnose the following
o If we cannot read the value AAH we need to check data bus
connections.
o If we cannot read the address 2000H, we need to check the addre ss bus
connections
o If output of decoder is asserted high, then we need to check th e address
line connections to the decoder chip.
o The control signals ܦܴതതതത and ܴܹതതതതത have to be active low to perform the
operation.
3.8 8085-Based Single-Board microcomputer
x When we turn on power, a monitor program is executed where prog ram
counter is reset to 0000H and hex code is loaded from there.
x The monitor program reads hex ke yboard and check for closure.
x It then display the key pressed at display and simultaneously s tores binary
equivalent memory.
x Finally transfer the program execution to user program as the E ;ECUTE
button is pressed.
3. Summary
x The 8085 microprocessor is dual inline package with 40 pins wit h each pin
having a unique functionality.
x The architecture of 8085 has functional groups that helps to ca rry the
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x Each instruction is executed in instruction cycle which compris es of several
machine cycle which comprises of several T-states.
x There is no direct relationship between the number of bytes of instruction and
the number of machine cycles required to decode that instructio n.
x In interfacing the memory, if all address lines are used then i t represents
absolute decoding and if few address lines are used its partial decoding and
this reduces hardware and generates foldback mirror which provi des multiple
addresses.
3.10 List of references
x Ramesh Gaonkar, “Microprocessor Architecture, Programming and
Applications with the 8085”, Fifth Ed ition, Penram International Publishing
(I) Private Limited.
x https://tutorialspoint.com
x https://www.brighthubengineering.com
x https://www.javatpoint.com
3.11 Unit End E[ercise
1. State the functions of the following pins: (i) ; 1 (ii) HLDA (iii) IO/ ܯഥ(iv)
ܣܶܰܫതതതതതതത (v) READ<
2. Illustrate the steps and timing of data flow for the instructio n MOV D, M
stored in memory location 2000H.
3. Illustrate the steps and timing of data flow for the instructio n LDA 4050H
stored in memory location 3000H.
4. How to interface the EPROM. What is the address decoding techni que &
state the memory address range"
5. How to test and troubleshoot memory interfacing circuit"

™™™
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U1IT-2
4
I/O INTERFACING
Unit Structure
4.0 Objectives
4.1 Introduction
4.2 Basic Interfacing Concepts
4.2.1 Peripheral I/O Instructions
4 . 2 . 2 I / O E x e c u t i o n
4.2.3 Device Selection And Data Transfer
4.2.4 Absolute vs Partial Decoding
4 . 2 . 5 I n p u t I n t e r f a c i n g
4.2.6 Interfacing I/Os Using Decoders
4.3 Interfacing Output Displays
4.3.1 Illustration: LED Display for Binary Data
4 . 3 . 2 I l l u s t r a t i o n : S e v e n - S e g m e n t L E D D i s p l a y a s a n O u t p u t D evice
4.4 I1TERFACI1G I1PUT DEVICES
4.4.1 Illustration: Data Input from DIP Switches
4.5 Memory –Mapped I /O
4.5.1 Execution of Memory- Related Data Transfer Instructions
4 . 5 . 2 I l l u s t r a t i o n : S a f e t y C o n t r o l S y s t e m U s i n g M e m o r y - M a p p e d
I/O Technique
4.5.3 Comparison of Memory-Mapped I/O and Peripheral I/O
4.6 Testing And Troubleshooting I/O Interfacing Circuits
4 . 6 . 1 D i a g n o s t i c R o u t i n e A n d M a c h i n e C y c l e s
4.7 Summary

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4.0 Objectives
x Illustrate the 8085 bus contents and control signals when OUT a nd I1
instructions are executed.
x Recognize the device (port) address of a peripheral-mapped I/O by analyzing
the associated logic circuit.
x Illustrate 8085 bus contents and control signal when memory- re lated
instructions (LDA, STA, etc) are executed.
x Recognize the device (port) address of a memory-mapped I/O by a nalyzing
the associated logic circuit.
x Explain the difference between the peripheral-mapped and memory -mapped
I/O techniques.
x Interface an I/O device to a microcomputer for a specified devi ce address by
using logic gates and MSI chips, such as decoders, latches, and buffers.
4.1 Introduction
Any application of a microprocessor based system requires the t ransfer of data
between external circuitry to t he microprocessor and microproce ssor to the external
circuitry User can give information to the microprocessor based s y s t e m u s i n g
keyboard and user can see the result or output information from the microprocessor
based system with the help of display device. The transfer of d ata between
keyboard and microprocessor, and microprocessor and display dev ice is called
input / output data transfer or I/O data transfer. This data tr ansfer is done with the
help of I / O ports.
4.1.1 Input port:-
It is used to read data from the input device such as keyboard . The simplest form
of input port is a buffer. The input device is connected to the m i c r o p r o c e s s o r
through buffer as shown in the figure. This buffer is a tri-sta te buffer and its output
is available only when enable si gnal is active. When microproce ssor wants to read
data from the input device (keyboard), the control signals from the microprocessor
activates the buffer by asserting enable input of the buffer. O nce the buffer is
enabled, data from input device is available on the data bus. M icroprocessor reads
this data by initiating read command.
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4.1.2 Output port : -
It is used to send data to the output device such as display fr om the microprocessor.
The simplest form of output port is a latch. The output device is connected to the
microprocessor through latch, a s shown in the figure, When micr oprocessor wants
to send data to the output device it puts the data on the data bus and activates the
clock signal of the latch, latching the data from the data bus at the output of latch.
It is then available at the output of latch for output device.
4.2 Basic Interfacing Concepts
The approach to designing an interfacing circuit for an I/O dev ice is determined
primarily by the instructions to be used for data transfer. An I/O device can be
interfaced with the 8085 microprocessor either as a peripheral I/O or as a memory-
mapped I/O.
In the peripheral I/O, the instructions I1/OUT are used for dat a transfer, and the
device is identified by an 8- bit address. In the memory-mapped I / O , m e m o r y -
related instructions are used for data transfer, and device is identified by a 16-bit
address.
However, the basic concepts in interfacing I/O devices are simi lar in both methods.
Peripheral I/O is described in the following section, and memor y- mapped I/O in
further section.
4.2.1 Peripheral I/O Instructions
The 8085 microprocessor has two instructions for data transfer between the
processor and the I/O device: I1 and OUT.
The instruction I1 (Code DB) inputs data from an input device ( such as a keyboard)
into accumulator, and the instruction OUT (Code D3) sends the c ontents of the
accumulator to an output device such as an LED display. These a re 2-byte
instructions, with the second byte specifying the address or th e port number of an
I/O device. For example, the OUT instruction is described as fo llows. Opcode Operand Description OUT 8- bit Port Address This is a two-byte instruction with the
hexadecimal opcode D3, and the second byte
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Typically, to display the accumulator at an output device (such as LEDs) with the
address, for example, 01H, the instruction will be written and stored in memory as
follows: Memory
Address Machine
Code Mnemonics Memory
Contents 2050 D3 OUT 01H :2050 11010011 D3H 2051 01 :2051 00000001 01H (1ote: The memory locations 2050H are chosen here arbitrarily f or the illustration.)
If the output port with the address 01H is designed as an LED d isplay, the
instruction OUT will display the contents of the accumulator at the port. The second
byte of this OUT instruction can be any of the 256 combinations of eight bits, from
00H to FFH. Therefore, the 8085 can communicate with 256 differ ent output ports
with device addresses ranging from 00H to FFH. Similarly, the i nstruction I1 can
be used to accept data from 256 different input ports. 1ow the question remains:
How does one assign a device address or a port number to an I/O device from
among 256 combinations" The decision is arbitrary and somewhat dependent on
available logic chips. To understand a device address, it is ne cessary to examine
how the microprocessor executes I1/OUT instructions.
4.2.2 I/O E[ecution
The execution of I/O instructions can best be illustrated using the example of the
OUT instruction given in the previous section (4.2.1). the 8085 executes the OUT
instruction in three machine cycles, and it takes ten T-states (clock periods) to
complete the execution.
Out Instruction (8085)
In the first machine cycle, M 1 (Opcode Fetch, Figure 4.1) the 8085 places the high-
order memory address 20H on A 15-A8 and the low-order address 50H on AD-AD 0.
At the same time, ALE goes high and IO/ M goes low. The ALE sig nal indicates
the availability of the address on AD 7-AD 0, and it can be used to demultiplex the
bus. The IO/M, being low, indicates that it is a memory-related operation. At T 2,
the microprocessor sends the ܦܴ c o n t r o l s ig n a l , w hi c h i s c o m b i n e d w i t h I O/ M
(externally, to generate the ( ܴܯܧܯ ) signal, and the processor fetches the
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When the 8085 decodes the machine code D3, it finds out that th e instruction is a
2- byte instruction and that it must read the second byte.
In the second machine cycle, M 2 (Memory Read), the 8085 places the next address,
2051 H, on the address bus and gets t he device address 01H via the data bus.
On the low –order (AD 7 - AD 0 ) as well as high-order (A 15 - A 8 ) address bus.
The IO/ Ṁ signal goes high to indicate that it is an I/O operation. At T 2, the
accumulator contents are placed on the data bus (AD 7 - AD 0), followed by the
control signal WR
By A1Ding the IO/ Ṁ and ܴܹ signals, the ܹܱܫ signal can be generated to enable
an output device.

Figure 4.1 : 8085 Timing for E[ecution of OUT Instruction
Figure 4.1 shows the execution timing of the OUT instruction. T he information
necessary for interfacing an output device is available during T2 and T 3 of the M 3
cycle. The data byte to be displayed is on data bus, 8- bit dev ice address is available
on the low- order as well as high-order address bus, and availa bility of the data byte
is indicated by the ܴܹ control signal. The availability of the device address on both
segments of the address bus i s redundant information in periph erals I/O, only one
segment of the address bus (low or high) is sufficient for inte rfacing. The data byte
remains on the data bus only for two T- states, then the proces sor goes on to execute
the next instruction. Therefore, the data byte must be latched now, before it is lost,
using the device address and control signal
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In Instruction
The 8085 instruction set includes the instruction I1 to read (c opy) data from input
devices such as switches, keyboard, and A/D data convertors. Th is is a two- byte
instruction that reads an input device and places the data in t he accumulator. The
first byte is the opcode, and the second byte specifies the por t address. Thus, the
addresses for input devices can range from 00H to FFH . The ins truction is
described as
I1 8- bit :- This is a two- byte instruction with the hexadecim al opcode DB, and
the second byte is the port address of an input device.
This instruction reads (copies) data from an input device and p laces the data byte
in the accumulator.
To read switch positions, for example, from an input port with the address 84H, the
instructions will be written and stored in memory as follows : Memory
Address Machine
Code Mnemonics Memory Contents 2065 DB I1 84H :2065 11011011 DBH 2066 84 :2066 10000100 84H (1ote: - The memory locations 2065H and 66H are selected arbit rary for the
illustration.)
When the microprocessor is asked to execute this instruction, i t will first read the
machine codes (or bytes) stored at locations 2065H and 2066H, t hen read the switch
positions at port 84H by enabling the interfacing device of the port. The data byte
indicating switch positions from the input port will be placed in the accumulator.
Figure shows the timing of the I1 instruction M 1 and M 2 cycles are identical to
that of the OUT instruction.
In the M 3 cycle, the 8085 microprocessor places the address of the input port (84H)
on the low- order address bus AD 7 –AD 0 as well as on the high- order address bus
A15 – A8 and asserts the ܦܴ signal, which is used to generate the I/O Read (IOR)
signal.
The ܴܱܫ enables the input port, and the data from input port are plac ed on the data
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Figure 4.2:- 8085 Timing for E[ ecution of IN Instruction
Machine cycles M 3 (Figure 4.2 ) is similar to the M 3 cycle of the OUT instruction
the only differences are (1) the control signal is ܦܴinstead of ܴܹ and (2) data flow
from an input port to the accumulator rather than from the accu mulator to an output
port.
4.2.3 Device Selection And Data Transfer
The objective of interfacing an output device is to get informa tion or a result out of
the processor and store it or display it. The OUT instruction s erves that purpose
during the M 3 cycle of the OUT instruction the processor places that informat ion
(accumulator contents) on the data bus. If we connect the data bus to a latch, we
can catch that information and display it via LEDs or a printer . 1ow the questions
are : (1) When should we enable the latch to catch that informa tion " and (2) What
should be the address of that latch " The answers to both quest ions can be found in
the M 3 cycle (Figure 4.1 ) .The latch should be enabled when IO/M is high and ܴܹ
is active low. Similarly, the address of an output port is also on the address bus
during M 3 (it is 01H in figure 4.1 ). 1ow the task is to generate one pu lse by
decoding the address bus (A 7 - A 0 or A 15 – A8) to indicate the presence of the port
address we are interested in, generate a timing pulse by combin ing IO/M and ܴܹ
signals to indicate that the data byte we are looking for is on the data bus, and use
these pulses (by combining them) to enable the latch. These ste ps are summarized
as follows. (For all subsequent discussion, the bus A 7- A 0 is assumed to be that
demultiplexed bus AD 7 – AD 0 ).
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1. Decode the address bus to generate a unique pulse correspon ding to the
device address on the bus this is called device address pulse or I/O address
pulse.
2. Combine (A1D ) the device address pulse with the control sig nal to generate
a device select (I/ O select) pulse that is generated only when both signals are
asserted.
3. Use the I/O select to activate the interfacing device (I/O port).
The block diagram (Figure 4.3 ) illustrate these steps for inte rfacing an I/O device.
In Figure 4.3, address lines A 7 - A 0 connected to a decoder, which will generate a
unique pulse corresponding to each address on the address lines . This pulse is
combined with the control signal to generate a device select pu lse, which is used to
enable an output latch or an input buffer.

Figure 4.3 :- Block Diagram of I/O Interface
Figure 4.4 shows a practical decoding circuit for the output de vice with address
01H. Address lines A 7 – A0 are connected to 8- input 1 A1D gate that functions as
a decoder. Lines A 0 is connected directly, and lines A 7 – A1 are connected through
the inverters. When the address bus carries address 01H, gate G 1 generates a low
pulse otherwise, the output remains high. Gate G 2 and the control signal ܹܱܫ to
generate an I/O select pulse when both input signals are low.

Figure 4.4:- Decoder Logic for LED Output Port
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Meanwhile the contents of the accumulator are placed on the dat a bus and are
available on the data bus for a few microseconds and, therefore , must be latched
for display. The I/O select pulse clocks the data into the latc h for display by the
LEDs.
4.2.4 Absolute vs Partial Decoding
In figure 4.4, all eight address lines are decoded to generate one unique output
pulse the device will be selected only with the address, 01H. This is called
absolute decoding and is a good design practice. However, to minimize the cost,
the output port can be selected by decoding some of the address lines, as shown in
figure  this is called partial decoding.
As a result, the device has multiple addresses (similar to fold back memory
addresses).

Figure 4.5 :- Partial Decoding : O utput Latch with Multiple Add resses
Figure 4.5 is similar to figure 4.4 except that the address lin es A 1 and A 0 are not
connected, and they are replaced by IO/ M and ܴܹ signals. Because the address
lines A 1 and A 0 are at don’t care logic level , they can be assumed to be 0 and 1.
Thus this output port (latch) can be accessed by the Hex addres ses 00, 01, 02 and
03. The partial decoding is a commonly used technique in small systems. Such
multiple addresses will not cause any problems, provided these addresses are not
assigned to any other output ports.
4.2.5 Input Interfacing
Figure 4.6 shows an example off interfacing an 8-key input port . The basic concepts
behind this circuit are similar t o the interfacing concepts exp lained earlier.
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Figure 4.6 :- Decode Logic for a Dip – switch Input Port
The address lines are decoded by using an 8- input 1A1D gate. W hen address lines
A7 – A0 are high(FFH), the output of the 1A1D gate goes low and is com bined
with control signal ܴܱܫ in gate G 2. When the MPU executes the instruction (I1
FFH), gate G 2 generates the device select pulse that is used to enable the t ri- state
buffer. Data from the key are put on the data bus D 7 – D0 and loaded into the
accumulator. The circuit for the input port in figure differs f rom the output port in
figure as follows:
1. Control signals ܴܱܫ is used in place of ܹܱܫ .
2. The tri-state buffer is used as an interfacing port in plac e of the latch.
3. In figure 4.6, data flow from the keys to the accumulator on the other hand,
in figure, data flow from the accumulator to the LEDs.
4.2.6 Interfacing I/Os Using Decoders
Various techniques and circuits can be used to decode an addres s and interface an
I/O device to the microprocessor. However, all of these techniq ues should follow
the three basic steps suggested in above section.
Figure 4.4 and 4.6 illustrate an approach to device selection u sing an 8- input
1A1D gate. Figure 4.5 illustrate a technique using minimum hard ware this
technique has the disadvantage of having multiple addresses for same device.
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Figure 4.7 :- Address Decodi ng Using 3-to-8 Decoder
Figure 4.7 illustrate another scheme of address decoding. In t his circuit, a 3- to- 8
decoder and a 4- input 1A1D gate are used to decode the address bus the decoding
of the address bus is the first step in interfacing I/O devices .
The address lines A2, A1 and A0 are used as input to the decode r, and the remaining
address lines A 7 – A3 are used to enable the decoder. The address lines A 7 is directly
connected to E 3 (active high Enable line), and the address lines A 6 – A3 are
connected to E 1 and E 2 (active low enable line) using the 1A1D gate. The decoder
has eight output lines thus, we can use this circuit to genera te eight device address
pulses for eight different addresses.
The second step is to combine t he decoded address with an appro priate control
signal to generate the I/O select pulse. Figure shows that the output O 0 of the
decoder is logically A1Ded in a negative A1D gate with the ܹܱܫ control signal.
The output of the gate is the I/O select pulse for an output po rt. The third step is to
use this pulse to enable the output port. Figure shows that the I / O s e l e c t p u l s e
enables the LED latch with the output port address F8H, as show n below (A 7 – A0
is the de multiplexed low- order bus).
Similarly, the output O 2 of the decoder is combined with I/O Read (IOR) signal,
and the I/O select pulse is used to enable the input buffer wit h the address FAH.


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4.3 Interfacing Output Displays
This section concerns the analysis and design of practical circ uits for data display.
The section includes two different types of circuits. The first illustrates the simple
display of binary data with LEDs, and the second illustrate the interfacing of seven-
segment LEDs.
4.3.1 IIIustration: LED Display for Binary Data
Problem Statement
1. Analyze the interfacing circuit in figure, identify the add ress of the output
port, and explain the circuit operation.
2. Explain similarities between (a) and (b) in figure.
3. Write instructions to display binary data at the port.
Circuit Analysis
Address bus A 7 – A0 is decoded by using an 8- input 1A1D gate. The output of
the 1A1D gate goes low only when the address lines carry the ad dress FFH. The
output of the 1A1D gate is combined with the microprocessor con trol signal ܹܱܫ
in a 1OR gate (connected as negative A1D).The output of 1OR gat e 74LS02 goes
to generate an I/O select pulse when both inputs are low (or bo th signals are
asserted). Meanwhile, the contents of accumulator have been put on the data bus.
The I/O select pulse is used as a clock pulse to activate the D - type latch, and the
data are latched and displayed.

Figure 4.8 :- Interfacing LED Output Port Using the 7475 D-Latc h (a) and
Using the 74LS373 Octal D-Type Latch (b)
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In this circuit, the LED cathodes are connected to the 4 output of the latch. The
anodes are connected to 5V through resistors to limit the curr ent flow through the
diodes. When the data line (for example D 0 ) has 1, the output 4 is 0 and the
corresponding LED is turned on. If the LED anode were connected to 4, its cathode
would be connected to the ground .In this configuration, the D flip-flop would not
be able to supply the necessary ground. In this configuration, the D flip-flop would
not be able to supply the nece ssary current to the LED.
Figure 4.8 uses the 74LS373 octal latch an interfacing device, and both circuit(a)
an (b) are functionally similar. The 74LS373 includes D-latches (flip-flops)
followed by tri-state buffers. This device has two control sign als: Enable (G) to
clock data in the flip-flops and Output Control (OC) to enable the buffers. In this
circuit, the 74LS373 is used as a latch therefore the tri- sta te buffers are enabled
by grounding the OC signal.
Program Address (LO) Machine Code Mnemonics Comments 00 3E MVI A,
DATA  Load accumulator with data 01 DATA 02 D3 OUT FFH  Output accumulator contents
to port FFH 03 FF 04 76 HLT  End of program
Program Dscription
Instruction MVI loads the accumulator with the data you enter, and instruction
OUT FFH identifies the LED port as the output device and displa ys the data.
4.3.2 Illustration: Seven- Segmen t LED Display as an Output Dev ice
Problem Statement
1. Design a seven-segment LED output port with the device addr ess F5H, using
a 74LS138 3 –to- 8 decoder, a 74LS20 4-input 1A1D gate, a 74LS02 1OR
gate, and a common anode seven- segment LED.
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3. Explain the binary codes required to display 0 to F Hex dig its at the seven-
segment LED.
4. Write instructions to display digit 7 at the port.
Hardware Description
The design problem specifies two MSI chips – decoder (74LS138) and the latch
74LS373 – and a common- anode seven-segment LED. The decoder and the lat ch
have been described in previous sections the seven-segment LED and its binary
code requirement are discussed below.
Seven- Segment Led
A seven- segment LED consists of seven light- emitting diode se gments and one
segment for the decimal point. These LEDs are physically arrang ed as shown in
Figure 4.9 (a) . To display a number, the necessary segments ar e lit by sending an
appropriate signal for current flow through diodes.

Figure 4. :- Seven-S egment LED : LED Segments(a) Common-Anode
LED(b) Common- Cathode LED (c)
For example, to display an 8, all segments must be lit. To disp lay 1, segments B
and C must be lit. Seven- segment LEDs is available in two type s: common cathode
and common anode. They can be represented schematically as in F igure 4.9 (b) and
(c). Current flow in these diodes should be limited to 20mA.
The seven segments, A through G, are usually connected to data lines D 0 through
D6, respectively. If the decimal-point segment is being used, dat a line D 7 is
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connected to DP otherwise it is left open. The binary code req uired to display a
digit is determined by the type of the seven-segment LED ( comm on cathode or
common anode ), the connections of the data lines, and the logi c required to light
the segment. For example, to display digit 7 at the LED in Figu re 4.10, the
requirements are as follows :


Figure 4.10:- Interfaci ng Seven-Segment LED
1. It is a common- anode seven- segment LED, and logic 0 is re quired to turn
on a segment.
2. To display digit 7, segments A, B and C should be turned on .
3. The binary code should be Data
Lines D7 D6 D5 D4 D3 D2 D1 D0
78H Bits ; 1 1 1 1 0 0 0 Segments 1C G F E D C B A The code for each digit can be determined by examining the conn ections of the data
lines to the segments and the logic requirements.
Interfacing Circuit and its Analysis
To design an output port with the address F5H, the address line s A 7 – A0 should
have the following logic: A7 A6 A5 A4 A3 A2 A1 A0 F5H 1 1 1 1 0 1 0 1
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This can be accomplished by using A 2, A1 and A 0 as input lines to the decoder. A 3
can be connected to active low enable E 1, and the remaining address lines can be
connected to E 2 through the 4- input 1A1D gate. Figure shows an output port wi th
the address F5H. The output O 5 of the decoder is logically A1Ded with the control
signal ܹܱܫ using the 1OR gate (74LS02). The output of the 1OR gate is th e I/O
select pulse that is used to enable the latch (74LS373). The co ntrol signal is ܹܱܫ
is generated by logically A1Ding IO / M and ܴܹ signals in the negative 1A1D
gate (physically OR gate 74LS32).
Instructions: The following instructions are necessary to display digit 7 at the
output port:
MVI A, 78H  Load seven- segment code in the accumulator
OUT F5H  Display digit 7 at port F5H
HLT End
The first instruction loads 78H in the accumulator 78H is bina ry code necessary to
display digit 7 at the common- anode seven- segment LED. The se cond instruction
sends the contents of the accumulator (78H) to the output port F5H. When the 8085
executes the OUT instruction, the digit 7 is displayed at the p ort as follows:
1. In the third machine cycle M 3 of the OUT instruction (refer the figure), the
port address F5H is placed on the address bus A 7 – A0 (it is also duplicated
on the high- order bus A 15 – A8, but we have used the low- order bus for
interfacing in this example).
2. The address F5H is decoded by the decoding logic (decoder a nd 4- input
1A1D gate), and the output O 5 of the decoder is asserted.
3. During T 2 of the M 3 cycle (see Figure ), the 8085 places the data byte 78H
from the accumulator on the data bus and asserts the ܴܹ signal.
4. In the Figure 4.10, when the ܹܱܫ signal is asserted, the output of the 1OR
gate 74LS02 goes high and enables the latch 74LS 373.
The data byte (78H), which is already on the data bus at th inp ut of the latch, is
passed on the output of the latch and displayed by the seven-se gment LED.
However, the byte is latched when the ܴܹ signal is de-asserted during T 3.
Current Requirements : The circuit in Figure uses a common- anode seven-
segment LED. Each segment requires 10 to 15 mA of current (I D max 19 mA) for
appropriate illumination. The latch can sink 24mA when the outp ut is low and can
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anode LED segments are turned on by zeros on the output of the latch. If common-
cathode seven segment LED were used in this circuit, the output of the latch would
have to be high to drive the segments. The current supplied wou ld be about 2.6mA,
which is insufficient to make the segments visible.
4.4 Interfacing Input Devices
The interfacing of input device is similar to that of interfaci ng output devices,
except with some differences in bus signals and circuit compone nts. We will follow
the same basic steps described in Section and timing diagram fo r the execution of
the I1 instruction shown in the Figure.
4.4.1 Illustration: Data Input from DIP Switches
In this section, we will analyze the circuit used for interfaci ng eight DIP switches,
as shown in Figure 4.11. The circuit includes the 74LS138 3- to - 8 decoder to
decode the low- order bus and the tri-state octal buffer (74LS2 44) to interface the
switches to the data bus. The port can be accessed with the add ress 84H  However,
it has multiple addresses, as explained below.
4.4.2 Hardware
Figure 4.11 shows the 74LS244 tri- state octal buffer used as a n interfacing device.
The device has two groups of four buffers each, and they are co ntrolled by active
low signal OE. When OE is low, the input data show up on the ou tput lines
(connected to the data bus), and when OE is high, the output l ines assume the high
impedance state.

Figure 4.11:- Interfacing DIP Switches

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4.4.3 Interfacing Circuit
Figure 4.11 shows that the low order address bus, except the li nes A 4 and A 3, is
connected to the decoder (the L74S138)  the address lines A 4 and A 3 are left in the
don’t care state.
The output line O 4 of the decoder goes low when the address bus has the following
address (assume the don’t care lines are at logic 0); A7 A6 A5 A4 A3 A2 A1 A0 84H 1 0 0 0 0 1 0 0 Enables lines Don’t Care Input
The control signal I/O Read ( IOR) is generated by A1Ding the I O / M (through
an inverter) and ܦܴ in a negative 1A1D gate, and the I/O select pulse is generated
by A1Ding the output of the decoder and the control signal ܴܱܫ . When the address
is 84H and the control signal ܴܱܫ is asserted, the I/O select pulse enables the tri-
state buffer and the logic levels of the switches are placed on the data bus.
The 8085, then, begins to read switch positions during T 3 (Figure) and places the
reading in the accumulator. When a switch is closed, it has log ic 0, and when it is
open, it is tied to 5V, representing logic 1.
Figure 4.11 shows that the switches S 7 –S3 are open and S 2 – S0 are closed thus,
the input reading will be F8H.
4.4.4 Multiple Port Addresses
In Figure 4.11, the address lines A 4 and A 3 are not used by the decoding circuit the
logic levels on these lines can be 0 or 1 .Therefore, this inpu t port can be accessed
by four different addresses, as shown below. A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 0 1 0 0 84H 0 1 8CH 1 0 94H 1 1 9CH 4.4.5 Instructions To Read Input Port
To read data from the input port shown in Figure, the instructi on I1 84H can be
used. When this instruction is executed, during the M 3 cycle, the 8085 places the
address 84H on the low- order bus (as well as on the high-order bus), asserts the
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4.5 Memory –Mapped I /O
In memory-mapped I/O, the input and output devices are assigned and identified
by 16- bit addresses. To transfer data between the MPU and I/O devices, memory-
related instructions (such as LDA, STA etc ) and memory control signals ( ܴܯܧܯ )
and ܹܯܧܯ ) are used.
The microprocessor communicates with an I/O device as if it wer e one of the
memory locations. The memory- mapped I/O technique is similar i n many ways to
the peripheral I/O technique. To understand the similarities, i t is necessary to
review how a data byte is transferred from the 8085 microproces sor to a memory
location or vice- versa. For example, the following instruction w i l l t r a n s f e r t h e
contents of the accumulator to the memory location 8000H. Memory
Address Machine Code Mnemonics Comments 2050 32 STA 8000H  Store contents of
accumulator in
memory location
8000H 2051 00 2052 80 (1ote : It is assumed here that the instruction is stored in me mory locations 2050H,
51H, and 52H ).
The STA is a three- byte instruction the first byte is the opc ode, and the second
and third bytes specify the memory address. However, the 16- bi t address 8000H
is entered in the reverse order  the low- order byte 00 is sto red in location 2051,
followed by the high-order address 80H ( the reason for the rev ersed order will be
explained in Section ). In this example, if an output device, i nstead of a memory
register, is connected at this address, the accumulator content s will be transferred
to the output device. This is called the memory- mapped I/O technique.
On the other hand, the instruction LDA (Load Accumulator Direct ) transfers the
data from a memory location to the accumulator. The instruction LDA is a 3-byte
instruction the second and third bytes specify the memory loca tion. In the memory-
mapped I/O technique, an input device (keyboard) is connected i nstead of a
memory. The input device will have the 16- bit address specifie d by the LDA
instruction.
When the microprocessor executes the LDA instruction, the accum ulator receives
data from the input device rather than from a memory location. To use memory-
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and Memory Write (MEMW) should be connected to I/O devices inst ead of ܴܱܫ
and ܹܱܫ signals, and the 16- bit address bus (A 15 – A0 ) should be decoded. The
hardware details will be described in section).
4.5.1 E[ecution of Memory- Related Data Transfer Instructions
The execution of memory-related data transfer instructions is s imilar to the
execution of I1 or OUT instructions, except that the memory-rel ated instructions
have 16-bit addresses.
The microprocessor requires four machine cycles (13 T-states) t o execute the
instruction STA (Figure 4.12). The machine cycle M 4 for the STA instruction is
similar to the machine cycle M 3 for the OUT instruction.
For example, to execute the instruction STA 8000H in the fourth machine cycle
(M4), the microprocessor places memory address 8000H on the entire address bus
(A15 - A 0 ) .The accumulator contents are sent on the data bus, followed by the
control signal Memory Write ܹܯܧܯ( active low).
On the other hand, in executing the OUT instruction (Figure), t he 8- bit device
address is repeated on the low- order address bus (A 0 – A7) as well as on the high-
order bus, and the ܹܱܫ control signal is used. To identify an output device, either
the low-order or the high-order bus can be decoded. In the case of the STA
instruction, the entire bus must be decoded.

Figure 4.12 :- Timing for E[ecu tion of the Instruction STA 8000 H
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Device selection and data transfer in memory-mapped I/O require three steps that
are similar to those required in peripheral I/O:
1. Decode the address bus to generate the device address pulse .
2. A1D the control signal with the device address pulse to gen erate the device
select (I / O select) pulse.
3. Use the device select pulse to enable the I/O port.
To interface a memory- mapped input port, we can use the instru ction LDA 16- bit,
which reads data from an input port with the 16-bit address and places the data in
the accumulator.
The instruction has four machine cycles only the fourth machin e cycle differs from
M4 in Figure 4.12. The control signal will be ܦܴrather than ܴ ,the data flow from
the input port to microprocessor.
4.5.2 Illustration: Safety Control System Using Memory-Mapped I /O
Technique
Figure 4.13 shows a schematic of interfacing I/O device using t he memory-mapped
I/O technique. The circuit includes one input port with eight D IP switches and one
output port to control various processes and gates, which are t urned on/off by the
microprocessor according to the corresponding switch positions.

Figure 4.13 :- Memory-Mapped I/O Interfacing
For example, switch S 7 controls the cooling system, and switch S 0 controls the exit
gate. All switch inputs are tied high therefore, when switch i s open (off), it has
5V and when a switch is closed (on), it has logic 0.
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The circuit includes 3 – to-8 decoder, one 8- input 1A1D gate, and one 4-input
1A1D gate to decode the address bus. The output O 0 of decoder is combined with
control signal ܹܯܧܯ to generate the device select pulse that enables the octal
latch. The output O 1 is combined with the control signal ( ܴܯܧܯ )to enable the
input port. The eight switches are interfaced using a tri-state buffer 74LS244, and
the solid state relays controlling various processes are interf aced using an octal
latch (74LS373) with tri-state output.
Output Port and its Address
The various process control devices are connected to the data b us through the latch
74LS373 and solid state relays. If an output bit of the 74Ls373 is high, it activates
the corresponding relays and turns on the process the process remains on until the
bit stays high. Therefore, to control these safety processes, w e need to supply an
appropriate bit pattern to the latch.
The 74LS373 is a latch followed by a tri-state buffer, as shown in Figure. The latch
and and the buffer are controlled independently by the Latch En able (LE) and
Output Enable (OE).
When LE is high, the data enter the latch, and when LE goes low , data are latched.
The latched data are available on the output lines of the 74LS3 73 if the buffer is
enabled by OE (active low ). If OE is high, the output lines g o into the high
impedance state.
Figure 4.13 shows that the OE is connected to the ground thus, the latched data
will keep the relays on/ off according to the bit pattern. The LE is connected to the
device select pulse, which is asserted when the output O 0 of the decoder and the
control signal ܹܯܧܯ go low .Therefore, to assert the I/O select pulse, the output
port address should be FFF8H, as shown below: A1
5 A1
4 A1
3 A1
2 A1
1 A1
0 A
9 A
8 A
7 A
6 A
5 A
4 A3
A
2 A
1 A
0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 FFF8
H To 8- input 1A1D gate to Enable E 2 To 4-input 1A1D
gate to Enable E 1 To
Enable
E3 Decoder
Input Input Port and its Address
The DIP switches are interfaced with the 8085 using the tri- st ate buffer 74LS244.
The switches are tied high, and they are turned on by grounding , as shown in
Figure. The switch positions can be read by enabling the signal OE, which is
asserted when the output O1 of th e decoder and the control sign al (ܴܯܧܯ )go low.
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82MICROPROCESSOR ARCHITECTUREA1
5 A1
4 A1
3 A1
2 A1
1 A1
0 A
9 A
8 A
7 A
6 A
5 A
4 A3
A
2 A
1 A
0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 FFF9
H To 8- input 1A1D gate to Enable E 2 To 4-input 1A1D
gate to Enable E 1 To
Enable
E3 Decoder
Input Instructions : - To control the processes according to switch positions, the
microprocessor should read the bit pattern at the input port an d send that bit pattern
to the output port.
The following instructions can accomplish this task:
READ : LDA FFF9H  Read the switches
CMA  Complement switch reading, convert on- switch (logic 0) i nto logic 1 to
turn on appliances
STA FFF8H  Send switch positions to output port and turn on/of f appliances.
JMP READ  Go back and read again
When this program is executed, the first instruction reads the bit pattern
1011 0111 (B7H) at the input port FFF9H and places that reading in the
accumulator this bit pattern represents the on- position of sw itches S 6 and S 3 . The
second instruction complements the reading  this instruction i s necessary because
the on-position has logic 0, and to turn on solid state relays logic 1 is necessary.
The third instruction sends the complemented accumulator conten ts ( 0100 1000
48H) to the output port FFF8H. The 74LS373 latches the data byt e 0100 1000 and
turns on the heating system and lights. The last instruction, J MP READ, takes the
program back to the beginning and repeats the loop continuously .Thus, it monitors
the switches continuously.
4.5.3 Comparison of Memory-Mapped I/O and Peripheral I/O Characteristics Memory-Mapped I/O Peripheral I/O 1. Device address 16- bit 8- bit 2. Control signals for
Input / Output (ܴܯܧܯ / )MEMW ܴܱܫ / ܹܱܫ 3. Instruction
available Memory-related instructions
such as STA LDA LDA;
STA; MOV M, R: ADD M
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83Chapter 4: I/O Interfacing4. Data transfer Between any register and I/O Only between I/O and
the accumulator 5. Maximum number
of I/Os possible The memory map (64K) is
shared between I/Os and
system memory The I/O map is
independent of the
memory map 256 input
devices and 256 output
devices can be
connected. 6. Execution speed 13 T-states (STA, LDA) 7 T-states (MOV M, R) 10 T-states 7. Hardware
requirements More hardware is needed to
decode 16-bit address Less hardware is needed
to decode 8-bit address 8. Other features Arithmetic or logical
operations can be directly
performed with I/O data 1ot available 4.6 Testing and Troubleshooting I/O Interfacing Circuits
In previous sections we illustrated how to interface an I/O dev ice to a working
microcomputer system or add an I/O port as an expansion to the existing system.
In section we designed the LED output port with the address F5H . The next step is
to test and verify that we can display the digit 7 by sending t he code 78H as
specified in the design problem. In the first attempt, the most probable outcome
will be that nothing is displayed or digit 8 is displayed irres pective of the code sent
to the port.
1ow we need to troubleshoot the interfacing circuit. The obviou s first step is to
check the wiring and the pin connections. After this preliminar y check, we need to
generate a constant and identifiable signal and check various p oints in relation to
that signal. We can generate such a signal by asking the proces sor to execute a
continuous loop, called a diagnostic routine.
4.6.1 Diagnostic Routine and Machine Cycles
We can use the same instructions for the diagnostic routine tha t we used in the
design problem however, to generate a continuous signal, we ne ed to add a Jump
instruction, as shown next.

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84MICROPROCESSOR ARCHITECTUREInstruction Bytes T- States Machine Cycles M1 M2 M3 START : MVI
A, 78H 2 7 (4, 3) Opcode
Fetch Memory
Read OUT F5H 3 10 (4, 3, 3) Opcode
Fetch Memory
Read I/O Write JMP START 3 10 (4, 3, 3) Opcode
Fetch Memory
Read Memory
Read
This loop has 27 T- states and eight operations (machine cycles ). To execute the
loop once, the microprocessor asserts the ܦܴ signal seven times ( the Opcode Fetch
is also a loop is executed in 8.9—s, and the ܴܹ signal is repeated every 8.9—s that
can be observed on a scope. If we sync the scope on the ܴܹܴܹ pulse from the
8085, we can check the output on a scope. If we sync the scope on the ܴܹ pulse
from the 8085, we can check the output of the decoder, ܹܱܫ ,and IOSEL signals
some of these signals of a working circuit are shown in Figure 4.14

Figure 4.14 :- Timing Signals of Diagnostic Routine
When the 8085 asserts the ܴܹ signal, the port address F5H must be on the address
bus A 7- A 0, and the output O 5 of the decoder in figure must be low. Similarly, the
ܹܱܫ must be low and the IOSEL (the output of the 74LS02) must be h igh. 1ow if
we check the data bus in relation to ܴܹ signal, one line at a time, we must read the
data byte 78H.If the circuit is not properly functioning, we ca n check various
signals in reference to the ܴܹ signal as suggested below:
1. If IOSEL is low, check ܹܱܫ and O 5 of the decoder .
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85Chapter 4: I/O Interfacing
2. If ܹܱܫ is high, check the input to the OR gate 74LS32 . Both should b e low.
3. If O 5 of the decoder is high, check all the output lines O 0 to O 7 of the decoder.
If all of them are high, that means the decoder is not enabled. If one of the
outputs of the decoder is low, it suggests that the input addre ss lines are
improperly connected.
4. If the decoder is not enabled, check the address lines A 4 – A7  all of them
must be high and the address line A 3 must be low.
5. Another possibility is that the port is enabled, but the se ven-segment display
is wrong .
The problem must be with data lines . Try different codes to dis play other digits. If
two data lines are interchanged, you may be able to isolate the se two data lines.
The final step is to check all the data lines.
4.7 Summary
In this chapter, we examined the machine cycles of the OUT and I1 instructions
and derived the basic concepts in interfacing peripheral-mapped I /Os. Similarly,
we examined the machine cycles of memory-related data transfer instructions and
derived the basic concepts in interfacing memory-mapped I/Os. T hese concepts
were illustrated with various examples of interfacing I/O devic es.
Peripheral-Mapped I/O
The OUT is a two-byte instruction. It copies (transfers or send s) data from the
accumulator to the addressed port.
When the 8085 executes the OUT instruction, in the third machin e cycle, it places
the output port address on the low-order bus, duplicates the sa me port address on
the high-order bus, places the contents of the accumulator on t he data bus, and
asserts the control signal ܴܹ
A latch is commonly used to interface output devices.
The I1 instruction is a two-byte instruction. It copies ( trans fer or reads) data from
an input port and places the data into the accumulator.
When the 8085 executes the I1 instruction, in the third machine cycle, it places the
input port address on the low-order bus, as well as on the high -order bus, asserts
the control signal ܦܴ ,and transfers data from the port to the accumulator.
A tri-state buffer is commonly used to interface input devices. munotes.in

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86MICROPROCESSOR ARCHITECTURE
To interface an output or an input device, the low- order addre ss bus A7 – A0 ( or
high- order bus A 15 – A8 ) needs to be decoded to generate the device address pulse,
which must be combined with the control signal ܴܱܫ ( or ܹܱܫ ) to select the device.
Memory-Mapped I/O
Memory-related instructions are used to transfer data.
To interface I/O devices, the entire bus must be decoded to gen erate the device
address pulse, which must be combined with the control signal ( ܴܯܧܯ( ) or
MEMW) to generate the I/O select pulse. This pulse is used to e nable the I/O device
and transfer the data.
4uestions and Problems
1. Explain why the number of output ports in the peripheral-ma pped I/O is
restricted to 256 ports.
2. In the peripheral-mapped I/O, can an input port and an outp ut port have the
same port address"
3. If an output and input port can have the same 8-bit address , how does the
8085 differentiate between the ports"
4. Specify the two 8085 signals that are used to latch data in an output port.
5. What are control signals nece ssary in the memory-mapped I/O "
6. Can the microprocessor differentiate whether it is reading from a memory-
mapped input port or from memory"
7. Specify the 8085 signals that are used to latch data in an input port.
8. Specify the type of pulse (high or low) required to latch d ata in the 7475.
Books and References
1. Computer System Architecture by M. Morris Mano, PHI Publica tion, 1998.
2. Structured Computer Organization by Andrew C. Tanenbaum, PH I
Publication.
3. Microprocessors Architecture, Programming and Application w ith 8085 by
Ramesh Gaonker, PE1RAM, Fifth Edition, 2012.

™™™
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Unit-2
5
INTRODUCTION TO 8085 ASSEMBLY
LANGUAGE PROGRAMMING
Unit Structure
5.0 Objectives
5.1 Introduction
5.2 The 8085 Programming Model
5.2.1 Programming Registers
5.3 Instruction Classification
5.3.1 The 8085 Instruction Set
5.4 Instruction and Data Format
5.4.1 Instruction Word Size
5 . 4 . 2 O p c o d e F o r m a t s
5 . 4 . 3 D a t a F o r m a t
5.5 How to Write Assemble, and Execute a Simple Program
5 . 5 . 1 I l l u s t r a t e P r o g r a m : A d d i n g T w o H e x a d e c i m a l 1 u m b e r s
5.5.2 How Does a Microproce ssor Differentiate Between
Data and instruction Code"
5.6 Overview of the 8085 Instruction Set
5.7 Summary
5.0 Objectives
x Explain the various functions of the registers in the 8085 prog ramming
model.
x Define the term flag and explain how the flags are affected
x Explain the terms operation code (opcode) and operand, and illu strate these
terms by writing instructions.
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x Classify the instructions in terms of their word size and speci fy the number
of memory registers required to store the instructions in memor y
x List the five categories of the 8085 instruction set.
x Define and explain the term addressing mode.
x Write logical steps to solve a simple programming problem.
x Draw a flowchart from the logical steps of a given programming problem.
x Translate the flowchart into mnemonics and convert the mnemonic s into Hex
code for a given programming problem.
5.1 Introduction
An Assembly program is a set of instructions written in the mne monics of a given
microprocessor. These instructions are commands to the micropro cessor to be
executed in the given sequence to accomplish a task. To write s uch programs for
the 8085 microprocessor, we should be familiar with the program ming model and
the instruction set of the microprocessor.
The 8085 instruction set is classified into five different grou ps : data transfer,
arithmetic, logic, branch, and machine control each of these g roups is illustrated
with examples. It also discusses the instruction format and var ious addressing
modes. A simple problem of adding to Hex numbers is used to ill ustrate writing,
assembling, and executing a program. The flowcharting technique and symbols are
discussed in the context of the problem. It concludes with a li st of selected 8085
instructions.
5.2 THE 8085 PROG RAMMING MODEL
5.2.1 Programming Registers
The 8085 programming model incl udes six registers, one accumu lator, and flag
register, as shown in Figure 5.1.In addition,it has two 16- bit registers: the stack
pointer and program counter. They are described briefly as foll ows. munotes.in

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89Chapter 5: Introduction to 8085 Assembly Language Programming Accumulator A (8) Flag Register (8) B (8) C(8) D (8) E (8) H (8) L(8) Stack Pointer (SP) (16) Program Counter (PC) (16) Data Bus Address Bus
Bidirectional 8-Lines Unidirectional 16-Lines
(a) D7 D6 D5 D4 D3 D2 D1 D0 S = AC P CY (b)
Figure 5.1: 8085 Programming Model (a) and Flag Register (b)

Registers
The 8085 has six general-purpose registers to store 8- bit data  these are identified
as B,C, D, E, H, and L, as shown in Figure 5.1. They can be com bined as register
pairs – BC, DE, and HL – to perform some 16- bit operations. The programmer can
use these registers to store or copy data into the registers by using data copy
instructions.
Accumulator
The accumulator is an 8- bit register that is part of the arith metic / logic unit (ALU)
. This register is used to store 8- bit data and to perform ari thmetic and logical
operations. The result of an ope ration is stored in the accumul ator. The accumulator
is also identified a register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other r egisters.
They are called =ero (=), Carry (C<), Sign (S), Parity (P),and Auxiliary (AC) flags
they are listed in Table 5.1 and their bit positions in the fla g register are shown in munotes.in

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90MICROPROCESSOR ARCHITECTURE
Figure 5.1(a) . The most commonly used flags are =ero, Carry an d Sign. The
microprocessor uses these flags to test data conditions.
For example, after an addition of two numbers, if sum in the ac cumulator is larger
than eight bits, the flip- flop used to indicate a carry – called the Carry flag (C<) is
set to one.
Table 5.1: THE 8085 Flags The following flags are set or reset after execution of an arit hmetic or logic
operation  data copy instructions do not affect any flags = – =ero The =ero flag is set t o 1 when the result is zero  othe rwise it is reset. C< – Carry: If an arithmetic operation results in a carry, the C< f lag is set 
otherwise it is reset. S – Sign : The Sign flag is set if bit D 7 of the result 1  otherwise it is reset. P – Parity : If the result has an even number of 1s, the flag is s et for an odd
number of 1s, the flag is reset. AC – Auxiliary Carry : In an arithmetic operation, when a carry is generated by
digit D 3 and passed to digit D 4, the AC flag is set. This flag is used internally for
BCD ( binary- coded decimal ) operations  there is no Jump ins truction
associated with this flag.
When an arithmetic operation re sults in zero, the flip- flop ca lled the =ero (=) flag
is set to one. Figure 5.1(a) shows an 8-bit register, called th e flag register, adjacent
to the accumulator. However, it is not used as a register five bit positions out of
eight are used to store the outputs the five flip-flops. The fl ags are stored in the 8-
bit register so that the programmer can examine these flags (da ta conditions ) by
accessing the register through an instruction.
These flags have critical importance in the decision- making pr ocess of
microprocessor. The conditions (set or reset) of the flag are tested through software
instructions.
For example, the instruction JC ( Jump on Carry) is implemented to change the
sequence of a program when the C< flag is set. The thorough und erstanding of
flags is essential in writing assembly language programs.
Program Counter (PC)
This 16- bit register deals with sequencing the execution of in structions. This
register is a memory pointer. Memory locations have 16- bit add resses, and that is
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91Chapter 5: Introduction to 8085 Assembly Language Programming
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory a ddress from which
the next byte is to be fetched. When a byte (machine code) is b eing fetched, the
program counter is incremented by one to point to the next memo ry location.
Stack Pointer (SP)
The stack pointer is also a 16- bit register used as a memory p ointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading a 16-bit a ddress in the stack pointer.
5.3 Instruction Classification
An instruction is a binary pattern designed inside a microproce ssor to perform a
specific function. The entire group of instructions called inst ruction set, determines
what functions the microprocessor can perform. The 8085mmicropr ocessor
includes the instruction set of its predecessor, the 8080A, plu s two additional
instructions.
5.3.1 The 8085 Instruction Set
The 8085 instruction can be classified into the following five functional categories:
data transfer (copy) operations, arithmetic operations, logical operations, branching
operations, and machine- control operations.
Data Transfer (Copy) Opertions
This group of instruction copies data from a location called so urce to another
location, called a destination, without modifying the contents of the source. The
term data transfer is used for this copying function .However, the term transfer is
misleading it creates the impression that the contents of sour ce are destroyed when,
in fact, the contents are retained without any modification. Th e various types of
data transfer (copy) are listed below together with examples of each type:
Table 5.2 : Data Transfer E[amples Types E[amples Between registers Copy the contents of register B into
register D Specific data byte to a register or a
memory location Load register B with data byte 32H
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92MICROPROCESSOR ARCHITECTURETypes E[amples Between a memory location and a
register From the memory location 2000H to
register B Between an I/O device and the
accumulator From an input keyboard to the
accumulator
Arithmetic Operations
These instructions perform ar ithmetic operation such as additi on, subtraction,
increment, and decrement.
1. Addition : - Any 8- bit number, or the contents of a register, or the co ntents
of a memory location can be added to the contents of the accumu lator and the
sum is stored in the accumulator. 1o two other 8- bit registers can be added
directly (e.g. the contents of register B cannot be added direc tly to contents
of register C).
The instruction DAD is exception it adds 16- bit data directl y in register
pairs.
2. Subtraction : - Any 8- bit number, or the contents of a register, or the co ntents
of a memory location can be subtracted from the contents of t he accumulator
and the result is stored in the accumulator.
The subtraction is performed in 2’s complement, and the results, if negative,
are expressed in 2’s complement. No two other registers can be subtracted
directly.
3. Increment / Decrement: - The 8- bit contents of a register or a memory
location can be incremented or decremented by 1.Similarly, the 16- bit
contents of a register pair (such as BC) can be incremented or decremented
by 1. These increment and decrement operations differ from addi tion and
subtraction in an important way i.e. they can be performed in a ny one of the
registers or in a memory location.
Logical Operations
These instructions perform various logical operations with the contents of the
accumulator.
1. AND, OR, E[clusive -OR :- Any 8- bit number, or contents of a register, or
of a memory location can be logically A1Ded,ORed, or Exclusive- ORed
with the contents of the accumulator. The results are stored in t h e
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93Chapter 5: Introduction to 8085 Assembly Language Programming
2. Rotate: - Each bit in the accumulator can be shifted either left or right to the
next position.
3. Compare: - Any 8-bit number, or the contents of a register, or memory
location can be compared for equality, greater than, or less th an, with the
contents of the accumulator.
4. Complement: - The contents of the accumulator can be complemented all
0s are replaced by 1s and all 1s are replaced by 0s.
Branching Opertions
This group of instructions alters the sequence of program execu tion either
conditionally or unconditionally.
1. Jump:- Conditional jumps are an important aspects of the decision-maki ng
process in programming. These instructions test for a certain c ondition (e.g.
=ero or Carry flag) and alter the program sequence when the con dition is met.
In addition, the instruction set includes an instruction called unconditional
jump.
2. Call, Return, and Restart:- These instructions change the sequence of a
program either by calling a subroutine or returning from a subr outine. The
conditional Call and Return instructions also can test conditio n flags.
Machine Control Opertions
These instructions control machine functions such as Halt, Inte rrupt, or do nothing.
Some important aspects of the instruction set are noted below:
1. In data transfer, the contents of the source are not destro yed only the contents
of the destination are changed. The data copy instructions do n ot affect the
flags.
2. Any register including memor y can be used for increment or decrement.
3. Arithmetic and logical operations are performed with the co ntents of the
accumulator.
4. A program sequence can be changed either conditionally or b y testing for a
given data condition.
5.4 Instruction and Data Format
An instruction is a command to the microprocessor to perform a given task on
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94MICROPROCESSOR ARCHITECTURE
called the operation code (opcode) and the second is the data t o be operated on,
called the operand. The operand (or data) can be specified in v arious ways. It may
include 8-bit (or 16- bit) data, an internal register, a memory location, or 8- bit (or
16- bit) address. In some instruc tions, the operand is implicit .
5.4.1 Instruction Word Si]e
The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions.
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, “byte” and “word” are synonym ous because it is an 8-bit
microprocessor. However, instructions are commonly referred to in terms of bytes
rather than words.
One- Byte Instructions
A 1- byte instruction includes the opcode and the operand in th e same byte. For
example:
Table 5.3: One- Byte Instructions Task Opcode Operand Binary
Code He[ Code Copy the contents of the
accumulator in register C MOV C,A 0100
1111 4FH Add the contents of register
B to the accumulator ADD B 1000
0000 80H Invert ( complement ) each
bit in the accumulator CMA 0010
1111 2FH These instructions are 1-byte in structions performing three dif ferent tasks. In the
first instruction, both operand re gisters are specified.
In the second instruction, the operand B is specified and the a ccumulator is
assumed. Similarly, in the third instruction, the accumulator i s assumed to be the
implicit operand. These instructions are stored in 8-bit binary format in memory
each requires one memory location.
Two-Byte Instructions
In a 2-byte instruction, the first specifies the operation code and thee second byte
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95Chapter 5: Introduction to 8085 Assembly Language Programming
Table 5.4 : Two-Byte Instructions Task Opcode Operand Binary
Code Hex Code Load an 8-bit
data byte in
the
accumulator MVI A,Data 0011 1110 DATA 3E Data First Byte Second
Byte Assume the data byte is 32H.The assembly language instruction i s written as
Mnemonics He[ Code
MVI A,32H 3E 32H
This instruction would require two memory locations to store in memory.
Three-Byte Instructions
In a 3-byte instruction, the first byte specifies the opcode, a nd the following two
bytes specify the 16-bit address. 1ote that the second byte is the low-order address
and the third byte is the high-order address. For example:
Table 5.5: Three-Byte Instructions Task Opcode Operand Binary
Code Hex
Code Transfer the
program sequence
to the memory
location 2085H JMP 2085H 1100 0011 1100 0011
0010 0000 C3 85
20 First byte Second byte
Third byte This instruction would three memory locations to store in memor y.
These commands are in many ways similar to our everyday convers ation. For
example, while eating in a restaurant, we may make the followin g requests and
orders:
1. Pass (the ) butter
2. Pass (the ) bowl.
3. (Let us) eat.
4. I will have combina tion 17 ( on the menu).
5. I will have what Susie ordered.
The first request specifies the exact item it is similar to th e instruction for loading
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The second request mentions the bowl rather than the contents, even though one is
interested in the contents of the bowl. It is similar to the in struction MOV C,A
where registers (bowls) are specified rather than data.
The third suggestion (let us eat) assumes that one knows what t o eat. It is similar
to the instruction Complement, which implicitly assumes that th e operand is
accumulator.
In the fourth sentence, the location of the item on menu is spe cified and not the
actual item. It is similar to the instruction: transfer the dat a byte from the location
2050H.
The last order (what Susie ordered) is specified indirectly. It is similar to an
instruction that specifies a memory location through the conten ts of a register pair.
These various ways of specifying data are called the addressing modes . Although
microprocessor instructions requi re one or more words to specif y the operands, the
notations and conventions used in specifying the operands have very little to do
with the operation of the microprocessor.
The mnemonic letters used to specify a command are chosen by th e manufacturer.
When an instruction is stored in memory, it is stored in binary code, the only code
the microprocessor is capable of reading and understanding. The conventions used
in specifying the instructions are valuable in terms of keeping u n i f o r m i t y i n
different programs and in writing assemblers. The important poi nt to remember is
that the microprocessor neither reads nor understands mnemonics or hexadecimal
numbers.
5.4. 2 OPCODE FORMATS
The microprocessor 8085 is an 8 bit microprocessor and has 8 bi t opcodes .Each
instruction has a unique opcode.
The opcode contains information regarding the operation, type o f operation to be
performed, registers to be used, flags. The opcode is fixed for each instruction.
1otations used in object code or OPCODE are:
Table: 5.6 (a) Opcode Formats Notations Meaning ddd Destination register(s) sss Source registers, ddd sss 111 A register
000 B register
001 C register munotes.in

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97Chapter 5: Introduction to 8085 Assembly Language ProgrammingNotations Meaning 010 D register 011 E register
100 H register
101 L register nnn Restart number 000 to 111
Table: 5.6 (b) Opcode Formats Notation Meaning yy An 8 bit binary data yyyy A 16 binary data unit x Register pair 0 BC 1 DE xx Register pair 00 BC 01 DE
10 HL
11 SP
(if PUSH/POP)PSW PP44 A 16 bit memory address
Table: 5.6 (c) Information operations Information operations Io Io Io Operation 0 0 0 Read/ set interrupt
mask 0 0 1 Immediate
operation R p 0 1 0 Load / store 0 1 1 Increment /
Decrement R p 1 0 0 Increment single
register 1 0 1 Decrement single
register 1 1 0 Immediate
operation on single
register 1 1 1 Register shifting /
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Table: 5.6 (d) Arithmetic logic unit operations Arithmetic logic unit operations AL AL AL Operation 0 0 0 ADD 0 0 1 ADD with carry 0 1 0 SUB 0 1 1 SUB with borrow 1 0 0 Logical A1D 1 0 1 ;-OR 1 1 0 Logical OR 1 1 1 Compare
Table: 5.6 (e) Branch condition Branch condition CB CB CB Operation 0 0 0 J1= 0 0 1 J= 0 1 0 J1C 0 1 1 JC 1 0 0 JPO 1 0 1 JPE 1 1 0 JP 1 1 1 JM
Table 5.6 (f) Branch condition Branch operation Bo Bo Bo Operation 0 0 0 Conditional return 0 0 1 Simple return /
Miscellaneous 0 1 0 Conditional Jump 0 1 1 Unconditional jump
/ Miscellaneous 1 0 0 Conditional CALL 1 0 1 Simple CALL /
Miscellaneous 1 1 0 Special A / L
operations 1 1 1 Special
unconditional jump
For all data transfer instructions except MOV instruction forma t the opcode is, 0 0 d d d Io Io Io Destination register Information operation munotes.in

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99Chapter 5: Introduction to 8085 Assembly Language Programming
5.4.3 Data Format
The 8085 is an 8- bit microprocessor, and it processes (copy, add, subtract, etc)
only binary numbers. However, the real world operates in decima l numbers and
languages of alphabets and characters. Therefore, we need to co de binary numbers
into different media.
Let us examine coding. What is letter “A”? It is a symbol representing a certain
sound in a visual medium that eyes can recognize. Similarly, we can represent or
code groups of bits into different media. In 8- bit processor s ystems, commonly
used codes and data formats are ASCII, BCD, signed integers, an d unsigned
integers.
ASCII Code – This is a 7 bit alphanumeric code that represents decimal numbers,
English alphabets, and nonprintable characters such as carriage return. Extended
ASCII is an 8- bit code.
The additional numbers (beyond 7- bit ASCII code) represent gra phical characters.
BCD Code – The term BCD stands for binary-coded decimal it is used for de cimal
numbers. The decimal numbering system has ten digits, 0 to 9. T herefore, we need
only four bits to represent ten digits from 0000 to 1001. The r emaining numbers,
1010 (A) to 1111(F), are considered invalid. An 8- bit register in thev8085 can
accommodate two BCD numbers.
Signed Integer - A signed integer is either a positive number or a negative
number. In an 8- bit processor, the most significant digit D 7, is used for the sign  0
represents the positive sign and 1 represent the negative sign. The remaining seven
bits D 6 – D0, represent the magnitude of an integer. Therefore, the largest positive
integer that can be processed by the 8085 at one time is 0111 1 111 (7FH)  the
remaining Hex number in this microprocessor are represented in 2’s complement
format.
Unsigned Integers- An integer without a sign can be represented by all the 8 bit i n
a microprocessor register. There fore, the largest number that c an be processed at
one time is FFH. However, this does not imply that the 8085 mic roprocessor is
limited to handling only 8- bit numbers.
1umbers larger than 8 bits (such as 16-bit or 24-bit numbers) a re processed by
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1ow let us examine how the microprocessor interrupts any number . Let us assume
that after performing some operations the result in the accumul ator is 0100 0001
(41H) . This number can have many interpretations:
(1) It is an unsigned number equivalent to 65 in decimal.
(2) It is BCD number representing 41 decimal
(3) It is the ASCII capital letter “A” or
(4) It is group of 8 bits where bits D 6 and D 0 turn on and the remaining bits turn
off output devices.
The processor processes binary bits it is up to the user to in terpret the result. In our
example, the number 41H can be displayed on a screen as an ASCII “A” or 41
BCD.
5.5 How to Write Assemble, a nd E[ecute a Simple Program
A Program is a sequence of instructions written to tell a compu ter to perform a
specific function. The instructions are selected from the instr uction set of the
microprocessor. To write a program, divide a given problem in s mall steps in terms
of the operations the 8085 can perfor m, then translate these st eps into instructions.
Writing a simple program of adding two numbers in the 8085 lang uage is illustrated
below.
5.5.1 Illustrate Program: Adding Two He[adecimal Numbers
Problem Statement
Write instructions to load the two hexadecimal numbers 32H and 48H in registers
A and B respectively. Add the numbers, and display the sum at t he LED output port
PORT1.
Problem Analysis
Even though this is a simple problem, it is necessary to divide the problem into
small steps to examine the process of writing programs. The wor ding of the
problem provides sufficient clues for the necessary steps. They are as follows:
1. Load the numbers in the registers.
2. Add the numbers.
3. Display the sum at the output port PORT1.
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Flowchart
The steps listed in the problem analysis and the sequence can b e represented in a
block diagram, called a flowchart. Figure shows such a flowchar t representing the
above steps. This is a simple flowchart, and the steps are self -explanatory.
Assembly Language Program















Figure 5.2: Flowchart: Adding Two Numbers
To write an assembly language program, we need to translate the blocks shown in
the flowchart into 8085 operations and then, subsequently into mnemonics. By
examining the blocks, we can classify them into three types of operations: Block 1
and 3 are copy operations  Block 2 in an arithmetic operation  and Block 4 is a
machine-control operation. To tra nslate these steps into assemb ly and machine
languages, you should review thee instruction set.

Start
Load 1 Hex
Numbers
Add Numbers
Display Sum
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102MICROPROCESSOR ARCHITECTURE
The translation of each block into mnemonics with comments is s hown as follows:
Block 1: MVI A, 32H Load register A with 32H
MVI B, 48H Load register B with 48H
Block 2: ADD B Add two bytes and save the sum in A
Block 3: OUT 01H Display accumulator contents at port 01H
Block 4 : HALT End
From Assembly Language to He[ Code
To convert the mnemonics into Hex code, we need to look up the code in the
8085 instruction set this is call ed either manual or hand asse mbly. Mnemonics He[ Code MVI A,32H 3E 32 2- byte instruction MVI B, 48H 06 48 2- byte instruction ADD B 80 1- byte instruction OUT 01H D3 01 2- byte instruction HLT 76 1- byte instruction
Storing In Memory and Converting From He[ Code to Binary Code
To store the program in R/ W memory of a single-board microproc essor and display
the output, we need to know the memory addresses and the output port address.
Let us assume that R/W memory ranges from 2000H to 20FFH, and t he system has
an LED output port with the address 01H. 1ow, to enter the prog ram:
1. Reset the system by pushing the RESET key.
2. Enter the first memory address using the Hex keys where the program should
be stored.
Let us assume it is 2000H.
3. Enter each machine code by pushing Hex keys. For example, t o enter the first
machine code, push the 3, E, and STORE keys. (The STORE key may be
labelled differently in different systems.) When you push the S TORE key,
the program will store the machine code in memory location 2000 H and
upgrade the memory address to 2001H.
4. Repeat Step 3 until the last machine code, 76H.
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103Chapter 5: Introduction to 8085 Assembly Language Programming
1ow the question is : How does th e Hex code get converted into binary code"
The answer lies with the Monitor program stored in Read- Only m emory (or
EPROM) of the microcomputer system. An important function of th e Monitor
program is to check the keys and convert Hex code into binary c ode. The entire
process of manual assembly is shown in Figure
In this illustrate example, the program will be stored in memor y as follows: Mnemonics He[ Code Memory
Contents Memory
Address MVI A, 32H 3E 32 0011 1110 0011 0010 2000 2001 MVI B,48H 06 48 0000 0110
0100 1000 2002 2003 ADD B 80 1000 0000 2004 OUT 01H D3 01 1101 0011 0000 0001 2005 2006 HLT 76 0111 1110 2007 This program has eight machine codes and will require eight mem ory locations to
store the program. The critical concept that needs to be emphas ized here is that the
microprocessor can understand and execute only the binary instr uctions (or data )
everything else (mnemonics, Hex code, comments) is for the conv enience of
human being.
E[ecuting the Program
To execute the program, we need to tell the microprocessor wher e the program
begins by entering the memory address 2000H. 1ow we can push th e Execute key
( or the key with a similar label ) to begin the execution. As soon as the Execute
function key is pushed, the microprocessor loads 2000H in the p rogram counter
and the program control is transferred from the Monitor program to our program.

Figure 5.3: Manual Assembly Process
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The microprocessor begins to read one machine code at a time, a nd when it fetches
the complete instruction, it executes that instruction. For exa mple, it will fetch the
machine codes stored in memory locations 2000H and 2001H and ex ecute the
instruction MVI A, 32H thus it will load 32H in register A. Th e ADD instruction
will add the two numbers, and the OUT instruction will display the answer 7A (32H
48H 7A) at the LED port. It continues to execute instructions until it fetches the
HLT instruction.
Recogning the Number of B ytes in An Instruction
Students who are introduced to an assembly language for the fir st time should hand
assemble at least a few small programs. Such exercises can clar ify the relationship
among instruction codes, data, memory registers, and memory add ressing. One of
the stumbling blocks in hand assembly is in recognizing the num ber of bytes in a
given instruction. The following clues can b used to recognize the number of bytes
in an instruction of the 8085 microprocessor.
1. One- byte instruction – A mnemonic followed by a letter ( or two letters )
representing the registers (such as A,B, C, D, E,H,L,M, and SP) is a one-byte
instruction.
Instructions in which registers are implicit are also one- byt e instructions.
E x a m p l e s : ( a ) M O V A , B  ( b ) D C ; S P ( c ) R R C
2. Two- byte instruction – A mnemonic followed by 8-bit (byte ) is a two- byte
instruction.
Examples: (a) MVI A, 8-bit (b) ADI 8-bit
3. Three-byte instruction- A mnemonic followed by 16-bit (also terms such as
adr or dble ) is a three-byte instruction.
In writing assembly language programs, we can assign memory add resses in a
sequence once we know the number of bytes in a given instructio n. For example, a
three-byte instruction has three Hex codes and requires three m emory locations in
a sequence.
In hand assembly, omitting a byte inadvertently can have a disa strous effect on
program execution, as explained in the next section.
5.5.2 How Does a Microprocessor Differentiate Between Data and Instruction
Code"
The microprocessor is a sequential machine. As soon as a microp rocessor- based
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105Chapter 5: Introduction to 8085 Assembly Language Programming
continues in a sequence, one code after another (one memory loc ation after another)
at the speed of its clock until the system is turned off ( or t he clock stops) . If an
unconditional loop is set up in a program, the execution will c ontinue until the
system is either reset or turned off.
1ow a puzzling questions is : How does the microprocessor diffe rentiate between
a code and data when both are binary numbers "
The answer lies in the fact that the microprocessor interprets the first byte it fetches
as an opcode.
When the 8085 is reset, its program counter is cleared to 0000H and it fetches the
first code from the location 0000H
In the example of the previous section, we tell the processor t hat our program
begins at location 2000H. The first code it fetches is 3EH. Whe n it decodes that
code, it knows that it is a two- byte instruction. Therefore, i t assumes that the
second code, 32H, is a data byte . If we forgot to enter 32H and enter the next code,
06H, instead, the 8085 will load 06H in the accumulator, interp ret the next code,
48H, as an opcode, and continue the execution in sequence. As a consequence, we
may encounter a totally unexpected result.
5.6 Overview of the 8085 Instruction Set
The 8085 microprocessor instruction set has 74 operation codes that result in 246
instructions. The set includes all the 8080A instructions plus two additional
instructions ( SIM an RIM, related to serial I/O) .
The following notations are used in the description of the inst ructions.
R 8085 8- bit register (A, B, C, D, E, H, L)
M Memory register (location)
Rs Register Source (A, B, C, D, E, H, L)
Rd Register Destination (A, B, C, D, E, H, L)
Rp Register Pair (BC, DE, HL, SP)
( ) Contents of
1. Data transfer (copy) instructions:
From register to register
Load an 8-bit number in a register
Between memory and register
Between I/O and accumulator
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Table 5.8 : Data transfer (copy) instructions Mnemonics Tasks 1. MOV Rd,Rs Copy data from source register Rs into destination register
Rd 2. MVI R, 8-bit Load 8-bit data in a register 3. OUT 8-bit
(port address) Send (write ) data byte from accumulator to an output
device 4. I1 8-bit
(port address) Accept (read) data byte from an input device and place it in
the accumulator. 5. L;I Rp, 16-bit Load 16- bit in a register pair MOV R,M Copy the data byte from a memory location ( source ) into
a register LDA; Rp Copy the data byte into the accumulator from a memory
location indicated by a register pair. LDA 16-bit Copy the data byte into the accumulator from a memory
location specified by 16- bit address. MOV M,R Copy the data byte from register into memory location. STA; Rp Copy the data byte from the accumulator into the memory
location indicated by a register pair. STA 16-bit Copy the data byte from the accumulator in the memory
location specified by 16- bit address
2. Arithmetic instructions:
Add
Subtract
Increment (Add 1)
Decrement (Subtract 1)
Table 5.: Arithmetic instructions Mnemonics Tasks ADD R Add the contents of a register to the contents of the
accumulator ADI 8-bit Add 8-bit data to the contents of the accumulator SUB R Subtract the contents of a register from the contents of the
accumulator. SUI 8-bit Subtract 8-bit data from the contents of the accumulator. I1R R Increment the contents of a register munotes.in

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107Chapter 5: Introduction to 8085 Assembly Language ProgrammingMnemonics Tasks DCR R Decrement the contents of a register I1; Rp Increment the contents of a register pair DC; Rp Decrement the contents of a register pair ADD M Add the contents of a memory location to the contents of the
accumulator SUB M Subtract the contents of a memory location from the contents
of the accumulator. I1R M Increment the contents of a memory location. DCR M Decrement the contents of a memory location.
3. Logical instructions:
AND
OR
;-OR
Compare
Rotate
Table 5.10: Logical instructions Mnemonics Tasks A1A R/M Logically A1D the contents of register/memory with the
contents of the accumulator. A1I 8-bit Logically A1D the 8-bit data with the contents of the
accumulator. ORA 8-bit Logically OR the contents of register/memory with the
contents of the accumulator. ORI 8-bit Logically OR the 8-bit data with the contents of the
accumulator. ;RA 8-bit Exclusive-OR the contents of register/memory with the
contents of the accumulator. ;RI 8-bit Exclusive-OR the 8-bit data with the contents of the
accumulator. CMA Complement the contents of the accumulator. RLC Rotate each bit in the accumulator to left position. RAL Rotate each bit in the accumulator including the carry to the
left position. RRC Rotate each bit in the accumulator including the carry to the
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108MICROPROCESSOR ARCHITECTUREMnemonics Tasks RAR Rotate each bit in the accumulator including the carry to the
right position. CMP R/M Compare the contents of register/ memory with the contents
of the accumulator for less th an, equal to, or more than. CPI 8-bit Compare 8-bit data with the contents of the accumulator for
less than, equal to, or more than.
4. Branch Instructions:
Change the program sequence unconditionally.
Change the program sequence if s pecified data conditions are me t.
Table 5.11: Branch Instructions Mnemonics Tasks JMP 16- bit address Change the program sequence to the location specified
by the 16- bit address. J= 16- bit address Change the program sequence to the location specified
by the 16-bit address if the =ero flag is set. J1= 16-bit address Change the program sequence to the location specified
by the 16- bit address if =ero flag is reset. JC 16-bit address Change the program sequence to the location specified
by the 16- bit address if Carry flag is set. J1C 16-bit address Change the program sequence to the location specified
by the 16- bit address if Carry flag is reset. CALL 16- bit address Change the program sequence to the location of a
subroutine. RET Return to the calling program after completing the
subroutine sequence.
5. Machine Control instructions:
Table 5.12: Machine Con trol instructions Mnemonics Tasks HLT stop processing and wait. 1OP Do not perform any operation. This set of instructions is a representative sample it does no t include various
instructions related to 16- bit data operations, additional Jum p instructions, and
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109Chapter 5: Introduction to 8085 Assembly Language Programming
5.7 Summary
This chapter described the data manipulation functions of the 8 085 microprocessor,
provided an overview of the instruction set, and illustrated th e execution of
instructions in relation to the system’s clock. The important concepts in this chapter
can be summarized as follows.
The 8085 microprocessor operations are classified into five maj or groups: data
transfer (copy), arithmetic, logic, branch, and machine control .
An instruction has two parts: opcode (operation to be performed ) and operand (data
to be operated on).
The operand can be data (8-bit or 16- bit), address, or registe r, or it can be implicit.
The method of specifying an operand (directly, indirectly, etc. ) is called the
addressing mode.
The instruction set is classified in three groups according to the word size : 1,2,3-
byte instructions.
To write an assembly language program, divide the given problem into small steps
in terms of the microprocessor operations, translate these step s into assembly
language instructions, and then translate them into the 8085 ma chine code.
4uestions and Programming Assignments
1. List the four categories of 808 5 instructions that manipula te data.
2. Define opcode and operand, and specify the opcode and the o perand in the
instruction MOV H,L.
3. Find the Hex codes for the following instructions, identify the opcodes and
operands, and show the order of entering the codes in memory.
a. STA 2050H b. J1= 2070H
4. Find the Hex machine code for the following instructions fr om the instruction
set, and identify the number of bytes of each instruction.
MVI B, 4FH  Load the first byte
MVI C,78H Load the second byte
MOV A,C  Get ready for addition
ADD B Add two bytes
OUT 07H  Display the result at port 7
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5. Assemble the following program, starting at location 2000H.
S T A R T : I 1 F 2 H  R e a d i n p u t s w i t c h e s a t p o r t F 2 H
C M A  S e t O 1 s w i t c h e s t o l o g i c 1 .
J= START  Go back and read i nput port if all switches are off .
6. Write logical steps to add the following two Hex numbers. B oth the numbers
should be saved for future use. Save the sum in the accumulator .
1umbers: A2H and 18H
7. Data byte 28H is stored in register B and data byte 97H is s tored in the
accumulator. Show the contents of register B, C, and the accumu lator after
the execution of the following two instructions:
MOV A,B
MOV C,A
Books and References
1. Computer System Architecture by M. Morris Mano, PHI Publica tion, 1998.
2. Structured Computer Organization by Andrew C. Tanenbaum, PH I
Publication.
3. Microprocessors Architecture, Programming and Application w ith 8085 by
Ramesh Gaonker, PE1RAM, Fifth Edition, 2012.

™™™
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Unit-2
6
INTRODUCTION TO 8085 INSTRUCTIONS
Unit Structure
6.0 Objectives
6.1 Introduction
6.2 Data Transfer (Copy) Opertions
6 . 2 . 1 A d d r e s s i n g M o d e s
6 . 2 . 2 I l l u s t r a t i v e P r o g r a m : D a t a T r a n s f e r – From Register to Output Port
6 . 2 . 3 I l l u s t r a t i v e P r o g r a m : D a t a T r a n s f e r t o C o n t r o l O u t p u t D evices
6.3 Arithmetic Operations
6 . 3 . 1 A d d i t i o n
6 . 3 . 2 I l l u s t r a t e P r o g r a m : A r i t h m e t i c O p e r a t i o n s –Addition and Increment
6.3.3 Subtraction
6 . 3 . 4 I l l u s t r a t i v e P r o g r a m : S u b t r a c t i o n o f T w o U n s i g n e d 1 u m b e rs
6.4 Logic Operations
6 . 4 . 1 L o g i c a n d
6.4.2 Illustrative Program: Data Masking with Logic And
6 . 4 . 3 O r , E x c l u s i v e - O r a n d 1 o t
6 . 4 . 4 S e t t i n g a n d R e s e t t i n g S p e c i f i c B i t s
6.4.5 Illustrative Program : Oring Data from Two Input Ports
6.5 Branch Operations
6.5.1 Unconditional Jump
6.5.2. Illustrative Program: Unconditional Jump to Set Up
A C o n t i n u o u s L o o p
6.5.3 Conditional Jumps
6.5.4 Illustrative Program: Testing of the Carry Flag
6.6 Writing Assembly Language Programs
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6 . 6 . 1 G e t t i n g S t a r t e d
6.6.2 Illustrative Program: Microprocessor – Controlled
M a n u f a c t u r i n g P r o c e s s
6 . 6 . 3 D o c u m e n t a t i o n
6.7 Debuging A Program
6.7.1 Debugging Machine Code
6.8 Summary
6.0 Objectives
x Explain the functions of data transfer (copy) instructions and how the
contents of the source register and destination register are af fected.
x Explain the Input/ output instructions and port addresses.
x Explain the functions of the machine control instructions HLT a nd 1OP
x Recognize the addressing modes of the instructions
x Draw a flowchart of a simple program
x Write a program in 8085 mnemonics to illustrate an application of data copy
instructions, and translate those mnemonics manually into their Hex code.
x Explain the arithmetic instructions, and recognize the flags th at are set or
reset for given data conditions.
x List the important steps in writing and troubleshooting a simpl e program.
6.1 Introduction
A microcomputer performs a task by reading and executing the se t of instructions
written in its memory. This set of instructions, written in a s equence, is called a
program. Each instruction in the program is a command, in binary, to the
microprocessor to perform an operation. This chapter introduces 8085 basic
instructions, their operati ons, and their applications.
It is concerned with using instructions within the constraints and capabilities of its
registers and the bus system. A few instructions are introduced from each of the
five groups (Data Transfer, Arithmetic, Logical, Branch, and Ma chine Control) and
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The simple illustrative programs given in this chapter can be e ntered and executed
on the single-board microcomputers used commonly in laboratorie s.
6.2 Data Transfer (Copy) Opertions
One of the primary functions of the microprocessor is copying d ata, from a register
( or I/O or memory) called the source, to another ( or I/O or m emory) called the
destination. The copying function is frequently labelled as the data transfer
function.
MOV : Move Copy a data byte.
MVI : Move Immediate Load a data byte directly.
OUT : Output to Port Send a data byte to an output device.
I1 : Input from Port Read a data byte from an input device.
The term copy is equally valid for input /output functions beca use the contents of
the source are not altered. However, the term data transfer is used so commonly to
indicate the data copy function, these terms are used interchan geably when the
meaning is not ambiguous.
In addition to data copy instructions, it is necessary to intro duce two-machine
control operations to execute programs.
HLT : Halt Stop processing and wait.
1OP : 1o Operation Do not perform any operation.
Instructions
The data transfer instructions copy data from a source into a d estination without
modifying the contents of the source. The previous contents of the destination are
replaced by the contents of the source.
In the 8085 processor, data transfer instructions do not affect the flags.
Table 6.1: Data Transfer (Copy) Operations Opcode Operand Description MOV Rd, Rs Move This is a 1-byte instruction
Copies data from source register Rs to destination
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114MICROPROCESSOR ARCHITECTUREOpcode Operand Description MVI R, 8- bit Move Immediate This is a 2-byte instruction
Loads the 8 bits of the second byte into the register
specified. OUT 8-bit port
address Output to Port This is a 2-byte instruction
Sends (copies) the contents of the accumulator (A) to
the output port specified in the second byte. I1 8-bit port
address Input from Port This is a 2-byte instruction
Accepts (reads) data from the input port specified in
the second byte, and loads into the accumulator. HLT Halt This is a 1-byte instruction
The processor stops executi ng and enters wait state
The address bus and data bus are placed in high
impedance state. 1o regis ter contents are affected. 1OP 1o Operation This is 1-byte instruction
1o operation is performed.
Generally used to increase processing time or
substitute in place of an instruction. When an error
occurs in a program and an instruction needs to
eliminated, it is more convenient to substitute 1OP
than to reassemble the whole program.
E[ample 6.1:- Load the accumulator A with data byte 82H ( H as Hexadecimal
number) and save the data in register B.
Instructions : MVI A, 82H
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The first instruction is a 2-byte instruction that loads the ac cumulator with the data
byte 82H, and the second instruction MOV B, A copies the conten ts of the
accumulator in register B without changing the contents of the accumulator.
E[ample 6.2 :- Write instructions to read eight O1/OFF switches connected to t he
input port with the address 00H, and turn on the devices connec ted to the output
port with the address 01H, as shown in Figure 6.1

Figure 6.1: Reading Data at Inpu t Port and Sending Data to Outp ut Port
Solution: - The input has eight switches that are connected to the data bus through
the tri-state buffer. Any one of the switches can be connected to 5V (logic 1) or
to ground (logic 0), and each switch controls the corresponding device at the output
port. The microprocessor needs to read the bit pattern on the s witches and send the
same bit pattern to the output port to turn on the correspondin g devices.
Instructions : I1 00H
OUT 01H
HLT
When the microprocessor executes the instruction I1 00H, it ena bles the tri-state
buffer. The bit pattern 4FH formed by the switch positions is p laced on the data bus
and transferred to the accumula tor. This is called reading an i nput port.
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When the microprocessor executes the next instruction, OUT 01H, it places the
contents of the accumulator on the data bus and enables the out put port 01H.The
output port latches the bit pattern and turns O1/ OFF the devic es connected to port
according to the pattern. In the Figure 6.1, the bit pattern 4F H will turn on the
devices connected to the output port data lines D 6, D3, D 2, D1, and D 0 . The space
heater and four light bulbs. To turn off some of the devices an d turn off some of
the devices and turn on the other devices, the bit pattern can be modified by
changing the switch positions.
For example, to turn on the radio and the coffeepot and turn of f all other devices,
the switches S 4 and S 5 should be on the others should be off. The microprocessor
will read the bit pattern 0011 0000, and this bit pattern will turn on the radio and
the coffeepot and turn off other devices.
The preceding explanation raises two questions:
1. What are second bytes in the instructions I1 and OUT"
2. How are they determined"
In answer to the first question, the second bytes are I/O port addresses. Each I/O
port is identified with a number or an address similar to the p ostal address of a
house. The second byte has eight bits, meaning 256 (28) combinations thus 256
input ports and 256 output ports with the addresses from 00H to F F H c a n b e
connected to the system.
The answer to the second questi on depends on the logic circuit used to connect and
identify a port by the system designer.
6.2.1 Addressing Modes
The above instructions are commands to the microprocessor to co py 8-bit data from
a source to destination. In thes e instruction source can be a r egister, an input port,
or an 8-bit number (00H to FFH) .S imilarly, a destination can b e register or an
output port.
The various formats of specifying the operands are called the a ddressing modes.
1. Immediate Addressing – MVI R, Data
2. Register Addressing - MOV Rd, Rs
3. Direct Addressing - I1 / OUT Port
The classification of the addressing modes is unimportant, exce pt that it provides
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117Chapter 6: Introduction to 8085 Instructions
For example, in the case of the MVI opcode, the letter I sugges ts that the second
byte is data and not a register. What is important is to become familiar with the
instructions.
6.2.2 Illustrative Program: Data Transfer – From Register to Output Port
Problem Statement
Load the hexadecimal number 37H in register B, and display the number at the
output port labelled PORT1.
Problem Analysis
Even though this is a very simple problem it is necessary to br eak the problem into
small steps and outline the thinking process in terms of the ta sks.
STEPS
Step 1 : Load register B with a number.
Step 2 : Send the number to the output port.
4uestions to be asked
Is there an instruction to load the register B" Is there an instruction to send the data from register B to the o u t p u t p o r t " 1 o
Review the instruction OUT. This instruction sends data from th e accumulator to
an output port.
The solution appears to be as follows: Copy the number from reg ister B into
accumulator A.
Is there an instruction to copy data from one register to anoth er register " MOV Rd, Rs.
Flowchart
The thinking process described here and the steps necessary to write the program
can be represented in a pictorial format, called a flowchart. F igure 6.2 describes
the preceding steps in a flowchart.
Flowcharting is an art. The flowchart in Figure 6.2 does not in clude all the steps
described earlier. Although the number of steps that should be represented in a
flowchart is ambiguous, not all of them should be included. It should represent a
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118MICROPROCESSOR ARCHITECTURE
A flowchart is a similar to the block diagram of a hardware sys tem or to the outline
of a chapter. Information in each block of the flowchart should be similar to heading
of a paragraph.













Figure 6.2 : Flowchart
Symbol commonly used in flowcharting are shown in Figure 6.3. T wo types of
symbols – rectangles and ovals – are already illustrated in Figure 6.2 . Arrow: Indicates the direction of the program
execution Rectangle: Represents a process or an operation Diamond : Represents a decision-making block Oval : Indicates the beginning or end of a
program
Start
Enter Number in a Register
Output Number
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119Chapter 6: Introduction to 8085 Instructions Double-sided rectangle : Represents a
predefined process such as a subroutine Circle with an arrow: Represents continuation
(an entry or exit ) to a different page. Figure 6.3: Flowcharting Symbols
The diamond is used with Jump instructions for decision making and the double-
sided rectangle is used for subroutine.
The flowchart in Figure 6.2 includes what steps to do and in wh at sequence. As a
rule, a general flowchart does not include how to perform these steps or what
registers are being used.
Assembly Language Program Tasks 8085 Mnemonics 1. Load register B with 37H MVI B, 37H 2.Copy the number from B to A MOV A, B 3. Send the number to output –port 01H OUT PORT1 4. End the program HLT Translation from Assembly Language to Machine Language
1ow, to translate the assembly language program into machine la nguage, look up
the hexadecimal machine codes for each instruction in the 8085 instruction set and
write each machine code in t he sequence, as follows : 8085 Mnemonics He[ Machine Code 1.MVI B, 37H 06 37 2.MOV A, B 78 3.OUT PORT1 D3 01 4.HLT 76
This program has six machine codes and will require six bytes o f memory to enter
the program into your system. If your single-board microprocess or has R/W
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120MICROPROCESSOR ARCHITECTURE
locations 2000H to 2005H. The format generally used to write an assembly
language program is shown below.
Program Format Memory Address
(He[) Machine Code
(He[) Instruction Opcode Operand Comments ;;00 06 MVI B, 37H Load register B with data
37H ;;01 37 ;;02 78 MOV A, B Copy(B) into (A) ;;03 ;;04 D3
PORT1 OUT PORT1 Display accumulator
contents (37H) at Port1 ;;05 76 HLT End of the program This program has five columns: Memory Address, Machine Code, Op code,
Operand and Comments.
Memory Address These are 16-bit addresses of the user (R/W) memory in the
system. Where the machine code of the program is stored. The be ginning address
is shown as ;;00 the symbol ;; represents the page number of t he available
R/W memory in the microcomputer, and 00 represents the line num ber.
Machine Code
The monitor program, which is stored in Read-only memory (ROM) of the
microcomputer, translates the Hex number into binary digits and stores the binary
digits in the R/W memory.
If the system has R/W memory with the starting address at 2000H and the output
port address 01H, the program will be stored as follows : Memory Address Memory Contents He[ Code 2000 0000 0110 06 2001 0011 0111 37 2002 0111 1000 78 2003 1101 0011 D3 2004 0000 0001 01 2005 0111 0110 76 munotes.in

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121Chapter 6: Introduction to 8085 Instructions
Opcode (Operation Code) :- An instruction is divided into two parts : Opcode and
Operand . Opcodes indicate the type of operation or function th at will be performed
by the machine code.
Operand: - The operand part of an instruction specifies the item to be pro cessed
it can be 8- bit or 16-bit data, a register, or a memory addres s.
An instruction, called mnemonic is formed by combining an opcod e and an
operand.
The mnemonics are used to write programs in the 8085 assembly l anguage and
then mnemonics in these programs are translated manually into t he binary machine
code by looking up in the instruction set.
Comments The comments are written as a part of the proper documentation of a
program to explain or elaborate th e purpose of the instruction used.
These are separated by a semicolon () from an instruction on s ame line.
How to Enter and E[ecute The Program
This program assumes that one output port is available on your microcomputer
system. The program cannot be executed without modification if your
microcomputer has no independent output ports other than the sy stem display of
memory address and data or if it has programmable I/O ports.
1. Push the Reset key.
2. Enter the 16-bit memory address of the first machine code o f your program.
3. Enter and store all the machine codes sequentially, using t he hexadecimal
keyboard on your system.
4. Reset the system.
5. Enter the memory address where the program begins and push the Execute
key.
If the program is properly entered and executed, the data byte 37H will be
displayed.
How to E[ecute a Program without an Output Port
If your system does not have an output port, either eliminate t he instruction OUT
PORT1, or substitute 1OP (1o Operation) in place of the OUT ins truction.
Assuming your system has R/W memory starting at 2000H, you can enter the
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122MICROPROCESSOR ARCHITECTUREMemory
Address Machine Code Mnemonic
Instruction 2000 06 MVI B, 37H 2001 37 2002 78 MOV A, B 2003 00 1OP 2004 00 1OP 2005 76 HLT After you have executed this program, you can find the answer i n the accumulator
by pushing the Examine Register Key
The program also can be executed by entering the machine code 7 6 in location
2003H, thus eliminating the OUT instruction.
6.2.3 Illustrative Program: Data Transfer to Control Output Dev ices
Problem Statement
A microcomputer is designed to control various appliances and l ights in your
house. The system has an output port with the address 01H, and various units are
connected to the D 7 to D 0 as shown in Figure 6.4. On a cool morning you want to
turn on the radio, the coffeepot, and space heater. Write appro priate instructions for
the microcomputer.
Assume the R/W memory in your system begins at 3000H.
Problem Analysis
The output port in Figure 6.4 is a latch (D flip-flop) .When da ta bits are sent to the
output port they are latched by the D flip-flop. A data bit at logic 1 supply
approximately 5V as output and can turn on solid-state relays.
To turn on the radio, the coffeepot and the space heater set D 6, D5, and D 4 at logic
1, and the other bits at logic 0. D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 0 0 70H The output port requires 70H, and it can be sent to the port by loading the
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123Chapter 6: Introduction to 8085 Instructions

Figure 6.4: Output Port to Control Devices
Program Memory Address Machine Code Mnemonic Instruction Comments 3000 3E MVI A,
70H Load the accumulator with the bit pattern
necessary to turn on the devices 3001 70 3002 D3 OUT 01H Send the bit pattern to the port 01H, and
turn on the devices 3003 01 3004 76 HLT End of the program
Program Output
The program simulates controlling of the devices connected to t he output port by
displaying 70H on a seven-segment LED display. If your system h as individual
LEDs, the binary pattern – 0111 0000- will be displayed.
6.3 Arithmetic Operations
The 8085 microprocessor performs various arithmetic operations, such as addition,
subtraction, increment, and decrement. These arithmetic operati ons have the
following mnemonics.
ADD : Add Add the contents of a regist er.
ADI : Add Immediate Add 8- bit data
SUB : Subtract Subtract the contents of a register.
SUI : Subtract Immediate Subtract 8-bit data.
I1R : Increment Increase the contents of a r egister by 1
DCR : Decrement Decrease the contents of a reg ister by 1.
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The arithmetic operations Add and Subtract are performed in rel ation to the
contents of the accumulator. However, the Increment or Decremen t operations can
be performed in any register.
Instructions
These arithmetic instructions (except I1R and DCR)
1. Assume implicitly that the accumulator is one of the operan ds.
2. Modify all the flags acco rding to the data conditions of th e result.
3. Place the result in the accumulator.
4. Do not affect the contents of the operand register.
The instructions I1R and DCR
1. Affect the contents of the specified register.
2. Affect all flags except the C< flag. Opcode Operand Description ADD R Add It is 1- byte instruction
Adds the contents of register R to the contents of the
accumulator. ADI 8-bit Add Immediate It is 2- byte instruction
Adds the second byte to the contents of the accumulator. SUB R Subtract It is 1- byte instruction
Subtracts the contents of register R from the contents of
the accumulator. SUI 8-bit Subract Immediate It is 2- byte instruction
Subtracts the second byte from the contents of the
accumulator. I1R R Increment It is a 1-byte instruction

Increases the contents of register R by 1
All flags except the C< are affected DCR R Decrement It is a 1-byte instruction

Decreases the contents of register R by 1
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125Chapter 6: Introduction to 8085 Instructions
6.3.1 Addition
The 8085 performs addition with 8-bit binary numbers and stores the sum in the
accumulator. If the sum is larger t han eight bits (FFH), it set s the Carry flag.
Addition can be performed either by adding the contents of a so urce register (B, C,
D, E, H, L, or memory) to the contents of the accumulator (ADD) or by adding the
second byte directly to the contents of the accumulator (ADI).
E[ample 6.3 :- The contents of the accumulator are 93H and the contents of
register C are B7H. Add both contents.
Instruction :- ADD C C< D7 D6 D5 D4 D3 D2 D1 D0 (A) 93  1 0 0 1 0 0 1 1 (C) B7 1 0 1 1 0 1 1 1 Carry 1 1 1 1 1 1 SUM(A) 14A 1 0 1 0 0 1 0 1 0
Flag Status: S 0, = 0, C< 1
When the 8085 adds 93H and B7H, the sum is 14AH it is larger t han eight bits, .
Therefore, the accumulator will have 4AH in binary, and the C< flag will be set.
The result in the accumulator (4AH) is not 0, and bit D 7 is not 1 therefore the =ero
and the Sign flags will be reset.
E[ample 6.4 :- Add the number 35H directly to the sum in the previous examp le
when the C< flag is set.
Instruction : - ADI 35H C< D7 D6 D5 D4 D3 D2 D1 D0 (A) 4AH  1 0 1 0 0 1 0 1 0 Data 35H 0 0 1 1 0 1 0 1 SUM(A) 7FH 0 0 1 1 1 1 1 1 1 Flag Status: S 0, = 0, C< 0
The addition of 4AH and 35H does not generate a carry and will reset the previous
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126MICROPROCESSOR ARCHITECTURE
Therefore, in adding numbers, it is necessary to count how many times the C< flag
is set by using some other programming techniques.
E[ample 6.5:- Assume the accumulator holds the data byte FFH. Illustrate the
difference in the flags set by adding 01H and by incrementing t he accumulator
contents.
Instruction :- ADI 01H C< D7 D6 D5 D4 D3 D2 D1 D0 (A) FFH  1 1 1 1 1 1 1 1 (Data) 01H 0 0 0 0 0 0 0 1 Carry 1 1 1 1 1 1 1 1 SUM(A) 100H 1 0 0 0 0 0 0 0 0
Flag Status: S 0, = 1, C< 1
After adding 01H to FFH the sum in the accumulator is 0 with a carry.
Therefore, the C< and = flags are set. Sign flag is reset becau se D 7 is 0.
Instruction I1R A
The accumulator contents will be 00H, the same as before. Howev er, the instruction
I1R will not affect the Carry flag it will remain in its previ ous status.
Flag Status: S 0, = 1, C< 1A
Flag Concepts And Cautions
After an operation, one or more flags may be set, and they can be used to change
the direction of the program sequence by using the Jump instruc tions. The
programmer should be alert for them to make a decision. If the flags are not
appropriate for the tasks, the programmer can ignore them.
Caution 1 :- In the Example 6.3, C< flag is set, and in Example 6.4, C< fla g is
reset. If programmer ignores the flag, it can be lost after the subsequent instructions.
The flag can be ignored when the programmer is not interested i n using it.
Caution 2 :- In Example 6.5, two flags are set. The programmer may use one or
more flags to make decisions or may ignore them if they are irr elevant.
Caution 3 :- The C< flag has a dual function  it is used as a carry in add ition and
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127Chapter 6: Introduction to 8085 Instructions
Carry Flag Set to 1 because the answer is larger than eight bits there is a carry
generated out of the last bit D 7. During the addition bits D 0 through D 6 may generate
carries but these carries do not affect the C< flag.
Misconception 1:- Bit D 0 in the result (4AH) corresponds to the bit position of
the Carry flag D 0 in the flag register, therefore, the Carry flag is reset.
Misconception 2 :- In the addition process, bits D 0 of 93H and B7H generate a
carry (or other bit additions generate carries ) therefore the Carry flag is set.
=ero Flag:- Reset to 0 because the answer is not zero. The =ero flag is se t only
when all eight bits in the result are 0.
Misconception 3 :- Bit D 6 in the result (4AH) is 1, and it corresponds to bit D 6
(zero flag position) in the fag register. Therefore, the = flag is set.
Sign Flag :- Reset to 0 because D 7 in the result is 0. The position of the sign flag
in the flag register is also D 7 . But it is just a coincidence. The microprocessor
designer could have chosen bit D 6 for the Sign flag and bit D 7 for the =ero flag in
the flag register. The Sign flag is relevant only when we are u sing signed numbers.
Misconception 4 :- If the Sign flag is set, the result must be negative.
6.3.2 Illustrate Program: Arithmetic Operations –Addition and Increment
Problem Statement
Write a program to perform the following functions, and verify the output.
1. Load the number 8BH in register D
2. Load the number 6FH in register C.
3. Increment the contents of register C by 1.
4. Add the contents of register C and D and display the sum at the output
PORT1.
Program
The illustrative program for arithmetic operations using additi on and increment is
presented as figure 6.5 to show the register contents during so me of the steps. munotes.in

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Figure 6.5: Illustrative Program for Arithmetic Operations-Usin g
Addition and Increment
Program Description
1. The first machine cycle codes load 8BH in register D and 6 FH in register C .
These are data copy instructions, so no flags are affected and they remain in
the previous state.
The status of the flags is shown ; to indicate no change in t heir status.
2. Instruction I1R C adds 1 to 6F H and changes the contents of C to 70H . The
result is nonzero and bit D 7 is zero therefore, the S and = flags are reset. The
C< flag is not affected by the I1R instruction,
3. To add ( C ) to (D), the contents of the registers must be t ransferred to the
accumulator because the 8085 cannot add two registers directly. T h e
instruction MOV A, C copies 70Hfrom C register into the accumul ator
without affecting (C).
4. Instruction ADD D, adds (D) to (A) stores the sum in A, and sets the Sign
flag as shown below:
(A) : 70H 0 1 1 1 0 0 0 0

(D) : 8BH 1 0 0 0 1 0 1 1
(A) : FBH 1 1 1 1 1 0 1 1
Flag Status: S 1, = 0, C< 0
5. The sum is displayed by the OUT instruction.
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Program Output
It will display FBH at the output port. If the output port is n ot available, the program
can be executed by entering the 1OP instructions in place of th e OUT instruction
and the answer FBH can be verified by examining the accumulator A. Similarly the
contents of registers C and D a nd the flags can be verified.
By examining the contents of the registers, following points ca n be confirmed:
1. The sum is stored in Accumulator
2. The contents of the source registers are not changed.
3. The Sign (S) flag is set.
Even though the Sign(S) flag is set, this is not a negative sum . The microprocessor
sets the Sign flag whenever an operation results in D 7 1 . T h e m i c r o p r o c e s s o r
cannot recognize whether FBH is a sum, a negative number, or a bit pattern.
In this example, the addition is not concerned with the signed numbers. With the
signed numbers, bit D 7 is reserved for a sign programmer and no number larger
than 127 10 can be entered.
6.3.3 Subtraction
The 8085 performs subtraction by using the method of 2’s complement.
The subtraction can be performed by using either the instructio n SUB to subtract
the contents of a source register or the instruction SUI to sub tract an 8- bit number
from the contents of the accumulator.
The 8085 performs the following steps internally to execute the instruction SUB
( or SUI)
Step1 : Converts subtrahend (the number to be subtracted) into its 1’s complement.
Step 2 : Adds 1 to 1’s complement to obtain 2’s complement of the subtrahend.
Step3: Add 2’s complement to the minuend (the contents of the accumulator)
Step 4: Complement the Carry flag
E[ample 6.6
Register B has 65H and the accum ulator has 97H. Subtract the co ntents of register
B from the contents of the accumulator.
Instruction: SUB B
Subtrahend (B) : 65H 0 1 1 0 0 1 0 1
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Step1:
1’s complement of 65H= 1 0 0 1 1 0 1 0
Step2:

Add 01 to obtain 0 0 0 0 0 0 0 1
2’s complement of 65H= 1 0 0 1 1 0 1 1

To subtract: 97H- 65H
Step 3:
Add 97H to 2’s complement of 65H= 1 0 0 1 0 1 1 1
2’s complement of 65H= 1 0 0 1 1 0 1 1
Carry 1 1 1 1 1
C< 1 0 0 1 1 0 0 1 0
C< 0 0 0 1 1 0 0 1 0
Step 4 : Complement Carry
Result (A) :32H
Flag Status: S 0, = 0, C< 0
If the answer is negative, it will be shown in the 2’s complement of the actual
magnitude.
For example, if the above subtraction is performed as 65H – 97H, the answer will
be the 2’s complement of 32H with the Carry ( Borrow) flag set.
6.3.4 Illustrative Program: Subtrac tion of Two Unsigned Numbers
Problem Statement
Write a program to do the following:
1. Load the number 30H in register B and 39H in register C.
2. Subtract 39H from 30H
3. Display the answer at PORT1
Program
The illustrative program for subtraction of two unsigned number s is presented as
Figure 6.6 to show the register contents during the steps. munotes.in

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Figure 6.6 : Illustrative Program: Subtraction of Two Unsigned Numbers
Program Description
1. Register B and C are loaded with 30H and 39H, respectively. The instruction
MOV A, B copies 30H into the accumulator. The contents of a reg ister can
be subtracted only from the contents of the accumulator and not from any
other register.
2. To execute the instruction SUB C the microprocessor perform s the following
steps
Step1:
39H 0 0 1 1 1 0 0 1
1’s complement of 39H= 1 1 0 0 0 1 1 0

Step2:

Add 01 to obtain 0 0 0 0 0 0 0 1
2’s complement of 39H= 1 1 0 0 0 1 1 1

To subtract: 30H- 39H
Step 3:
Add 30 H to 2’s complement of 39H 0 0 1 1 0 0 0 0
2’s complement of 39H= 1 1 0 0 0 1 1 1
BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB
C< 0 1 1 1 1 0 1 1 1
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Step 4: Complement carry
C< 1 1 1 1 1 0 1 1 1 F7H

3. The number F7H is a 2’s complement of the magnitude (39H – 30H) 09H.
4. The instruction OUT display F7H at PORT1.
Program Output
In this program, the unsigned numbers were used to perform the subtraction.
There is no way to differentiate between a straight binary number and 2’s
complement by examining the answer at the output port. The flag s are internal and
not easily displayed. However, a programmer can test the Carry flag by using the
instruction Jump On Carry (JC) and can find a way to indicate the answer is in 2’s
complement.
6.4 Logic Operations
The 8085instruction set includes logic functions such as A1D, O R, Ex OR, and
1OT (complement) . The opcodes of these operations as follows : A1A: A1D Logically A1D the contents of a register A1I: A1D Immediate Logically A1D 8-bit data ORA: OR Logically OR the contents of a register ORI: OR Immediate Logically OR 8-bit data ;RA: ;-OR Exclusive –OR the contents of a register. ;RI: ;-OR Immediate Exclusive-OR 8-bit data.
All logic operations are performed in relation to the contents of the accumulator.
Instructions
1. Implicitly assume that the accumulator is one of the operan ds.
2. Reset (clear) the C< flag .The instruction CMA is an except ion it does not
affect any flags.
3. Modify the =, P, and S flags according to the data conditio ns of the result.
4. Place the result in the accumulator.
5. Do not affect the contents of the operand register.
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133Chapter 6: Introduction to 8085 InstructionsOpcode Operand Description A1A R Logical A1D with Accumulator This is a 1- byte instruction
Logically A1Ds the contents of the register R with the
contents of accumulator.
8085 : C< is reset and AC is set. A1I 8-bit A1D Immediate with Accumulator This is a 2- byte instruction
Logically ORs the second byte with the contents of
accumulator
8085 : C< is reset and AC is set. ORA R Logical OR with Accumulator This is a 1- byte instruction
Logically ORs the contents of the register R with the
contents of accumulator ORI 8-bit OR Immediate with Accumulator This is a 2- byte instruction
Logically ORs the second byte with the contents of
accumulator ;RA R Logical Exclusive-OR with Accumulator
This is a 1- byte instruction
Exclusive-OR the contents of the register R with the
contents of accumulator. ;RI 8-bit Exclusive-OR Immediate with Accumulator This is a 2- byte instruction
Exclusive-ORs the second byte with the contents of
accumulator CMA Complement Accumulator This is a 1-byte instruction that complements the
contents of accumulator
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6.4.1 Logic AND
The process of performing logic operations through the software i n s t r u c t i o n s i s
slightly different from the hardwired logic. The A1D gate is sh own in Figure 6.7(a)
has two inputs and one output
On the other hand, the instruction A1A simulates eight A1D gate s, as shown in
Figure 6.7(b) .
For example, assume that register B holds 77H and the accumulat or A holds 81H.
The result of the instruction A1A B is 01H and is placed in the a c c u m u l a t o r
replacing the previous contents as shown in figure 6.7 (b)

Figure 6.7(a) Gate (b) a simulated ANA Instruction
Figure 6.7(b) shows that each bit of register b is independentl y A1Ded with each
bit of the accumulator, thus simulating eight 2- input A1D gate s.
6.4.2 Illustrative Program: Data Masking with Logic AND
Problem Statement
To conserve energy and to avoid an electrical overload on a hot a f t e r n o o n ,
implement the following procedures to control the appliances th roughout the
house(figure 6.8) . Assume that the control switches are locate d in the kitchen, and
they are available to anyone in the house. Write the instructio n to
1. Turn on the air conditioner if switch S 7 of the input port 00H is on.
2. Ignore all other switches of the input port even if someone attempts to turn
on other appliances.
Problem Analysis
In this problem we are interested in only one switch positions, S7, which is
connected to data line D 7. Assume that various persons in the family have turned
on the switches of the air conditioner (S 7 ), the radio (S 4), and the lights ( S 3, S2, S1,
S0 ).
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If the microprocessor reads the input port (I1 00H), the accumu lator will have data
byte 9FH .This can be simulated by using the instruction MVI A, 9FH .However,
if we are interested in knowing only whether switch S 7 is on, we can mask bits D 6
through D 0 by A1Ding the input data with a byte that has 0 in bit position s D 6
through D 0 and 1 in the position D 7 .
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 80H
After bits D 6 through D 0 have been masked, the remaining byte can be sent to the
output port to simulate turning on the air conditioner.
Program Memory Address Machine Code Instruction Opcode Operand Comments HI-LO ;;00 3E MVI A, Data This instruction simulates
the instruction I1 00H 01 9F 02 E6 A1I 80H Mask all the bits except D 7 03 80 04 D3 OUT 01H Turn on the air conditioner
if S 7 is on. 05 01 06 76 HLT End of program Program Output
The instruction A1I 80H A1Ds the accumulator data as follows: (A) 1 0 0 1 1 1 1 1 (9FH) A1D (Masking Byte 1 0 0 0 0 0 0 0 (80H) BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB (A) 1 0 0 0 0 0 0 0 (80H)
Flag Status: S 1, = 0, C< 0
The A1Ding operation always reset the C< flag. The result (80H) will be placed
in accumulator and then sent to output port, and the logic 1 of data bit D 7 turns on
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The masking is a commonly used technique to eliminate unwanted bits in abyte.
The masking byte to be logically A1Ded is determined by placing 0s in bit
positions that are to be masked and by placing 1s in the remain ing bit positions.
6.4.3 OR, E[clusive-OR and NOT
The instruction ORA (and ORI) simulates logic ORing with eight 2- input OR gate
 this process is similar to that of A1Ding The instruction ;RA (and ;RI) performs
Exclusive ORing of eight bits, and the instruction CMA inverts bits off the
accumulator.
E[ample 6.7:- Assume register B holds 93H and the accumulator holds 15H.
Illustrate the results of the instruction ORA B, ;RA B, and CMA .
1. The instruction ORA B will perform the following operation: (B) 1 0 0 1 0 0 1 1 (93H) OR (A) 0 0 0 1 0 1 0 1 (15H) BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB (A) 1 0 0 1 0 1 1 1 (97H) Flag Status: S 1, = 0, C< 0
The result 97H will be placed in the accumulator, the C< flag w ill be reset, and the
other flags will be modified to re flect the data conditions in the accumulator.
2. The instruction ;RA B will perform the following operation. (B) 1 0 0 1 0 0 1 1 (93H) ;-OR (A) 0 0 0 1 0 1 0 1 (15H) BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB (A) 1 0 0 0 0 1 1 0 (86H) Flag Status: S 1, = 0, C< 0
The result 86H will be placed in the accumulator and flags will be modified as
shown.
3. The instruction CMA will result in (A) 0 0 0 1 0 1 0 1 (15H) CMA BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB (A) 1 1 1 0 1 0 1 0 (EAH) The result EAH will be place d in the accumulator and no flags w ill be modified. munotes.in

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6.4.4 Setting And Resetting Specific Bits
At the various times, we may want to set or reset a specific bi t without affecting
the other bits. OR logic can used to set the bit, and A1D logic can be used to reset
the bit.
E[ample 6.8 :- In Figure 6.8, keep the radio on (D 4) continuously without affecting
functions of other appliances, even i f someone turns off the sw itch S 4 .

Figure 6.8:- Input Port To Control Appliances
Solution:- To keep the radio on without affecting the other appliances, th e bit D 4
should be set by ORing the reading of the input port with the d ata byte 10H as
follows : I1 00H (A) D7 D6 D5 D4 D3 D2 D1 D0 ORI
10H 0 0 0 1 0 0 0 0 BBBBBBBBBBBBBBBBBBBBBBBBBB
BBBBBBBBBBBBBBBBBBBBBBBBBB (A) D7 D6 D5 1 D3 D2 D1 D0
Flag Status: C< 0  other will depends on data
The instruction I1 reads the switch positions shown as D 7 – D0 and the instruction
ORI sets the bit D 4 without affecting any other bits.
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E[ample 6.:- In the Figure 6.8, assume it is winter and turn off the air co nditioner
without affecting the other appliances.
Solution :- To turn off the air conditioner, reset bit D7 by A1Ding the rea ding of
the input port with the data byte 7FH as follows : I1 00H (A) D7 D6 D5 D4 D3 D2 D1 D0 A1I 7FH 0 1 1 1 1 1 1 1 BBBBBBBBBBBBBBBBBBBBBBBBBB
BBBBBBBBBBBBBBBBBBBBBBBBBB (A) 0 D6 D5 D4 D3 D2 D1 D0
Flag Status: C< 0  other will depends on data
The A1I instruction resets bit D 7 without affecting the other bits.
6.4.5 Illustrative Program : ORin g Data From Two Input Ports
Problem Statement
An additional input port with eight switches and the address 01 H (Figure 6.9) is
connected to the microcomputer shown in the Figure 6.8 to contr ol the same
appliances and lights from the bedroom as well as from the kitc hen. Write
instructions to turn on the devices from any of the input ports .

Figure 6. Two Input Ports to Control Output Devices

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Problem Analysis
To turn on the appliances from any one of the input ports, the microprocessor needs
to read the switches at both ports and logically OR the switch positions.
Assume that the switch positions in one input port correspond t o the data byte 91H
and the switch positions in the second port correspond to the d ata byte A8H. The
person in the bedroom wants to turn on the air conditioner, the radio, and the
bedroom light and the person in the kitchen wants to turn on t he air conditioner,
the coffeepot, and the kitchen light. By ORing these two data b ytes the
microprocessor can turn on the necessary appliances.
To test this program, we must simulate the reading of the input port by loading the
data into register – for example, into B and C.
Program Memory Address Machine Code Instruction Opcode Operand Comments HI-LO ;;00 06 MVI B, 91H This instruction simulates
reading input port 01H 01 91 02 0E MVI C, A8H This instruction simulates
reading input port 00H 03 A8 04 78 MOV A, B It is necessary to transfer data
byte fro B to A to OR with C.
Band C cannot be ORed
directly. 05
B1 ORA C Combine the switch positions
from register B and C in the
accumulator. 06 D3 OUT PORT Turn on appliances and light 07 PORT1 08 76 HLT End of program PROGRAM OUTPUT
By logically ORing the data bytes in registers B and C (B) (A) 1 0 0 1 0 0 0 1 91H ( C) 1 0 1 0 1 0 0 0 A8H BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB (A) 1 0 1 1 1 0 0 1 (B9H) munotes.in

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Flag Status: S 1, = 0, C< 0
Data byteB9H is placed in the accumulator that turns on the air conditioner, radio,
coffeepot, and bedroom and kitchen lights.
6.5 BRANCH OPERATIONS
The branch instructions are most powerful instructions because they allow the
microprocessor to change the sequence of a program, either unco nditionally or
under certain test conditions. These instructions are key to th e flexibility and
versatility of a computer.
Branch instructions instruct the microprocessor to go to a diff erent memory
location, and the microprocess or continues executing machine co des from that new
location.
The address of the new memory location is either specified expl icitly or supplied
by the microprocessor or by extra hardware. They are classified in three categories:
1. Jump instructions
2. Call and Return instructions
3. Restart instructions
The Jump instructions specify the memory location explicitly. T hey are 3-byte
instructions: one byte for the operation code followed by a 16 -bit memory address.
Jump instructions are classified into two categories Unconditio nal Jump and
Conditional Jump.
6.5.1 Unconditional Jump
The 8085 instruction set includes one unconditional jump instru ction. The
unconditional Jump instruction enables the programmer to set up continuous loops.
Instruction Opcode Operand Description JMP 16-bit Jump It is 3-byte instruction
The second and third bytes specify the 16-bit memory
address.
Second byte low-order and third-byte high- order memory
address. For example, to instruct the microprocessor to go the memory lo cation 2000H, the
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141Chapter 6: Introduction to 8085 InstructionsMachine Code Mnemonics C3 00
20 JMP 2000H The 16 –bit memory address of the jump location is entered in the rever se order,
the low-order byte(00H) first, followed by the high-order byte( 20H)
6.5.2. Illustrative Program: Unconditional Jump to Set Up a Con tinuous Loop
Problem Statement
Modify the program in Example6.2 to read the switch positions c ontinuously and
turn on the appliances accordingly.
Problem Analysis
One of the major drawbacks of the program in Example 6.2 is tha t the program
reads switch positions once and then stops. Therefore, if you w ant to turn on/off
different appliances, you have to reset the system and start al l over again. This is
impractical in real-life situations. However, the unconditional Jump instruction, in
place of the HLT instruction, will allow the microcomputer to m onitor the switch
positions continuously. Memory
Address Machine Code Label Mnemonics Comments 2000 DB START I1 00H Read input switches 2001 00 2002 D3 OUT 01H Turn on devices according to
switch position 2003 01 2004 C3 JMP START Go back to beginning and
read the switches again 2005 00 2006 20
Program Format
The program includes one more column called label . The memory location 2000H
is defined with the label START  therefore, the operand of the jump instruction
can be specified by the label START. The program sets up the en dless loop, and
the microprocessor monitors the input port continuously. The ou tput will reflect
any change in the switch positions.
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6.5.3 Conditional Jumps
Conditional Jump instructions allow the microprocessor to make decisions based
on certain conditions indicated by the flags. After logic and a rithmetic operations,
flip-flops (flags) are set or reset to reflect data conditions. The conditional Jump
instructions check the flag conditions and make decisions to ch ange the sequence
of a program.
Flags
The 8085 flag register has five flags, one of which (Auxiliary Carry) is used
internally.
The other four flags used by the Jump instructions are
1. Carry flag
2. =ero flag
3. Sign flag
4. Parity flag
Two Jump instructions are associated with each flag. The sequen ce of a program
can be changed either because the condition is present or becau se the condition is
absent.
For example, while adding the numbers we can change the program sequence either
because the carry is present (JC Jump on Carry) or because car ry is absent
(J1C Jump On 1o Carry).
Instructions
All conditional Jump instructions in 8085 are 3-byte instructio ns the second byte
specifies the low-order (line number) memory address, and the t hird byte specifies
the high-order (page number) memory address.
The following instructions transfer the program sequence to the memory location
specified under the given conditions. Opcode Operand Description JC 16-bit Jump on Carry (if result generate carry and C< 1) J1C 16-bit Jump on 1o Carry ( C< 0) J= 16-bit Jump on =ero (if result is zero and = 1) J1= 16-bit Jump on 1o =ero( = 0) JP 16-bit Jump On Plus (if D 7 0 and S 0) JM 16-bit Jump On Minus (if D 7 0 and S 0) JPE 16-bit Jump On Even Parity (P 1) JPO 16-bit Jump On Odd Parity (P 0) munotes.in

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All the Jump instructions are listed here. =ero and Carry flags and related Jump
instructions are used frequently.
6.5.4 Illustrative Program: Testing of the Carry Flag
Problem Statement
Load the hexadecimal number 9BH and A7H in register D and E, re spectively, and
add the numbers. If the sum is greater than FFH, display 01H at output PORT0
otherwise, display the sum.
Problem Analysis And Flowchart
The problem can be divided into the following steps:
1. Load the numbers in the registers.
2. Add the numbers
3. Check the sum.
Is the sum ! FFH, go to step 4, else go to step 5
4. Get ready to display 01
5. Display
6. End
Flowchart and Assembly Language Program
The six steps listed above can be converted into a flowchart an d assembly language
program as shown in Figure 6.10

Figure 6.10: Flowchart And Assembly Language Program to Test C arry Flag
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Step 3 is a decision-making block. In a flowchart, the decision -making process is
represented by a diamond shape.
It is important to understand how this block is translated into the assembly language
program.
1. Is there a Carry
2. If the answer is no, change the sequence of the program. In the assembly
language this is equivalent to JUMP On 1o Carry –J1C.
3. 1ow the next question is where to change the sequence – to Step 5.At this
point exact location is not known, but it is labelled DSPLA<.
4. The next step in the sequence is 4 .Get ready to display by te 01H.
5. After completing the straight line sequence, translate Step 5 and Step 6 :
Display at the port and halt.
Machine Code with Memory Addresses
Assuming R/W memory begins at 2000H, the preceding assembly lan guage
program can be translated as follows: Memory Address Machine Code Label Mnemonics 2000 16 START: MVI D, 9BH 2001 9B 2002 1E MVI E, A7H 2003 A7 2004 7A MOV A, D 2005 83 ADD E 2006 D2 J1C DSPLA< 2007 ; 2008 ; 2009 3E MVI A, 01H 200A 01 200B D3 DISPLA<: OUT 00H 200C 00 200D 76 HLT
While translating into machine code, we leave memory locations 2007H and 2008H
blank because the exact locations of the transfer is not known. What is known is
that two bytes should be reserved for the 16-bit address. After c o m p l e t i n g t h e
straight line sequence, we know the memory address of the label D S P L A < i . e .
200BH. This address must be placed in the reversed order as sho wn:
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145Chapter 6: Introduction to 8085 Instructions
Using the Instruction Jump On Carry (JC)
1ow the question remains : Can the same problem be solved b usi ng the instruction
Jump On Carry (JC) " To use instruction JC, exchange the places of the answers

Figure 6.11: Flowcharts for I nstruction JUMP ON CARRY
The flowchart will be as be as in Figure 6.11, and it shows tha t the program
sequence is changed if there is a Carry. This flowchart has two end points : thus it
will require a few more instructions than that of the Figure 6. 10.In this particular
example, it is unimportant whet her to use instruction JC or J1C , but in most cases
the choice is made by the logic of a problem.
6.6 Writing Assembly Language Programs
Writing a program is equivalent to giving commands to the micro processor in a
sequence to perform a task.
6.6.1 Getting Started
Perform a Task. What is the task you are asking to do"
Sequence .What is the sequence you want it to follow"
Commands What are commands (inst ruction set) it can understand"
These terms can be translated into the steps as follows:
Step 1 : Read the problem carefully.
Step 2 : Break it down into small steps.
Step 3 : Represent these steps in a possible sequence with a flowchar t – a plan
of attack.
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Step 4 : Translate each block of the flowchart into appropriate mnemo nic
instructions.
Step 5 : Translate mnemonics into the machine code.
Step 6 : Enter the machine code in memory and execute. Only on rare
occasions is a program successfully executed on the first attem pt.
Step 7 : Start troubleshooting (debug a program).
6.6.2 Illustrative Program: Microprocessor –Controlled Manufacturing
Process
Problem Statement
A microcomputer is designed to monitor various processes on the floor of a
manufacturing plant, presented schematically in Figure 6.12.It has two input ports
with the addresses F1H and F2H and output port with address F3H .
Input port F1H has six switches, five of which D 4 –D0 control the conveyer belts
through the output port F3H.
Switch S 7, corresponding to the data line D 7, is reserved to indicate an emergency
on the floor. Input port F2H is controlled by the foreman, and its switch S 7’ is used
to indicate an emergency. Output line D 6 of port F3H is connected to the emergency
alarm.

Figure 6.12: Input /Output Ports to control Manufacturing Proce sses
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Write a program to
1. Turn on the five conveyer belts according to the O1/ OFF po sitions of the
switches S 4 – S0 at port F1H.
2. Turn off the conveyer belts and turn on the emergency alarm only when both
switches –S7 from port F1H and S 7’ from the port F2H – are triggered.
3. Monitor the switches continuously.
Problem Analysis
To perform the task specified in the problem, the microprocesso r needs to
1. Read the switch positions.
2. Check whether switches S 7 and S 7’ from the ports F1H and F2H are on.
3. Turn on the emergency signal if both switches are on, and t urn off all the
conveyer belts.
4. Turn on the conveyer belts according to the switch position s S0 through S 4 at
input port F1H if both the switches, S 7 and S 7’ are not on simultaneously.
5. Continue checking the switch positions.
The five steps listed above can be translated into a flowchart and an assembly
language program as shown in the Figure 6.13
Flowchart and Program

Figure 6.13: Flowchart and Program for Controlling
Manufacturing Processes
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6.6.3 Documentation
A program is similar to a circuit diagram. Its purpose is to co mmunicate to others
what the program does and how it does it. Appropriate comments are critical for
conveying the logic behind a program. The program as a whole sh ould be self-
documented.
From Assembly Language To Machine Code Mnemonics Machine Code Memory Addresses 1. START: I1 F1H DB F1 2000 2001 2. MOV B, A 78 (1) 2002 3. I1 F2H DB F2 2003 2004 4. A1I 80H E6 80 2005 2006 5. MOV C, A 4F 2007 6. MOV A, B 78 2008 7. A1I 80H E6(2) 2009 8. A1A C A1 200A 9. J1= SHTDW1 C2(3) 20
14 200B 200C
200D 10. MOV A, B 78 200E 11. A1I 1FH E6 1F 200F 2010 12. OUT F3H D3 F3 2011
2012 13. JMP START 14. SHTDW1: MVIA, 40H C3(4) 3E
40 2013 2014
2015 15. OUT F3H D3(5) 2016 16. HLT 76 2017 This program includes the several errors, indicated by the () b esides the code.
Program E[ecution
The above machine codes can be loaded in R/W memory, starting w ith memory
address 2000H.The execution of the program can be done in two w ays. The first is
to execute the entire code by pressing the Execute key, and sec ond is to use the munotes.in

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149Chapter 6: Introduction to 8085 Instructions
Single-Step key executes one instruction at a time, and by exam ining Register key
and flags as each instruction is being executed.
6.7 DEBUGING A PROGRAM
Debugging is a program is similar to troubleshooting hardware. It is essential to
search carefully for the errors in the program logic, machine c ode, and execution.
Static Debugging is similar to visual inspection of a circuit board it is done by a
paper- and pencil check off a flowchart and machine code.
Dynamic Debugging involves observing the output, or register co ntents, following
the execution of each instruction(Single-Single technique) or o f a group of
instructions (the breakpoint technique).
6.7.1 Debugging Machine Code
Translating the assembly language to the machine code is simila r to building a
circuit from a schematic diagram the machine code will have er rors just as would
the circuit.
The following errors are common:
1. Selecting a wrong code.
2. Forgetting the second or third byte of an instruction.
3. Specifying the wrong jump instruction.
4. 1ot reversing the order of high and low bytes in a Jump ins truction
5. Writing memory addresses in decimal, thus specifying wrong jump
instructions.
6.8 Summary
The instructions from 8085 instruction set include Data transfe r instructions such
as MOV, MVI, I1, OUT instruction. These instructions copy the c ontents of the
source into the destination without affecting the source regist er.
Arithmetic Instructions such as ADD, ADI, SUB, SUI, I1R, DCR an d Logic
Instructions such as A1A, A1I, ORA, ORI, ;RA, ;RI, CMA. The res ults of
arithmetic and logic operations a re usually placed in the accum ulator.
The conditional Jump instructions are executed according to th e flags set after an
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4uestions and Programming Assignments
41) Explain data transfer operations with examples.
42) Write instructions to load the hexadecimal number 65H in r egister C, and
92H in the accumulator A. Display the number 65 at PORT0 and 92 H in
PORT1.
43) Explain Arithmetic operations with examples.
44) Write a program using the ADI instruction to add the two h exadecimal
numbers 3AH and 48H and to display the answer at an output port .
45) Explain Logic operations with examples.
46) Explain branch operations with examples.
Books and References
1. Computer System Architecture by M. Morris Mano, PHI Publica tion, 1998.
2. Structured Computer Organization by Andrew C. Tanenbaum, PH I
Publication.
3. Microprocessors Architecture, Programming and Application w ith 8085 by
Ramesh Gaonker, PE1RAM, Fifth Edition, 2012.

™™™
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U N I T 3
7
PROGRAMMING TECHNI4UES WITH
ADDITIONAL INSTRUCTIONS
Unit Structure
7.1 Objectives
7.2 Introduction
7.3 Looping, Counting And Indexing
7.4 Additional Data Transfer And 16-Bit Arithmetic Instructions &Arithmetic
Instruction Related To Memory.
7.5 Logic Operations: Rotate,Logics Operations: Compare, Dynam ic
Debugging.
7.1 Objectives
At the end of this unit, the student will be able to
z Write the program on Looping
z Write the program on 16 bit arithmetic Instructions
z Illustrate various Data transfer instructions
z Describe the concept of rotate, compare instructions and dynami c debugging
7.2 Introduction
1. The 8085 instruction set incl udes equivalents of the 8086
2. An instruction is a binary pattern designed inside a microp rocessor to perform
a specific function.
3. As it is tedious and error inductive to recognize and write instruction in binary
languages these instructions are written in hexadecimal code.
4. Each manufacturer of a microprocessor has devised a symboli c code for each
instruction called Mnemonic.
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5. The mnemonic for a particular instruction consists of letter s and suggest the
operation to be performed by that instruction.
6. The mnemonic for a particular instruction consists of lette rs and suggest the
operation to be performed by that instruction.
Table 1 Equivalent Binary and He[adecimal code for Mnemonic Binary Code Hexadecimal Code Mnemonic 00111100 3C I1R A 10000000 80 ADD B 7. Machine Language- The instruction in binary coded form or hexadecimal
coded form are called machine code. A program written using mac hine code
(only 0 & 1) is called machine language program
8. Assembly Language- The program can also be written using m nemonic
operation codes & symbolic address for writing instructions and the data
using different notations I.e binary,decimal,hexadecimal etc. T his is called
assembly language, program written in assembly language has to be
translated in to a machine language. A translator, which transl ates an
assembly program in to a machine language program is known as a ssembler.
9. Mnemonics can be written by hand on a paper and translated manually in
hexadecimal code by looking in to the opcode sheet or table. Th is is called
hand assembly.
10. Then the program can be feed in to the microprocessor kit fo r execution
starting from the first address of RAM(Random Access Memory).
11. Assembly language program (Source Code) -------------! Hand Assembly----
------! Machine Language Program
12. The 8085 has 74 instructions and 246 binary patterns.
13. The entire group of instructions that a microprocessor suppo rts is called
instruction set.
14. Each instructions is represented by an 8-bit binary value.
15. These 8-bits of binary value i s called op-code or instructio n.
16. Classification of Instruction set
16.1 Data Transfer Group - This group of instructions copies data from a
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16.2 Arithmetic Group-This group of instructions perform operations such
as addition, substraction, decrement, or data in register or in memory
location
16.3 Logical Group-This group of instructions perform logical opera tions
such as A1D, OR E;-OR, compare, rotate complement with contents
of the accumulator. Then the result is stored in accumulator.
16.4 Branch Control Group- This group of instruction that change th e
sequence of program execution using conditional and uncondition al
jumps, subroutine call, Return and Restart
16.5 Stack I/O and Machine Control Group- This group of instruction
includes set of those instructi on which can be able to perform function
on stack.
7.3 Looping, Counting And Inde[ing
1. Looping- In this technique, the program is instructed to ex ecute certain set of
instructions repeatedly to execute a particular task number of times.
2. Counting- This technique allows programmer to count how man y times the
instruction/set of instructions are executed.
3. Indexing- This technique allows programmer to point or refe r the data stored
in sequential memory location one by one.

Fig 1 Generali]ed Programming Flowchart
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4. Example 1 Write a program to store ‘FFH’ in 20 continuous memory
locations starting at 4500H. Instruction L;I H,4500H MVI C, 14h UP: MVI M, FFh I1; H DCR C J1= UP HLT
The program listed above will continuously add data FF h in mem ory location
starting at 4500H.
First Instruction- L;I H will load the address 4500 H address i n H & L
Second Instruction- MVI C will load data 14h in Register C
Third Instruction- Will Copy data FFH in M(H & L) Register cont inuously with
labelled loop UP
Fourth instruction- Increment Memory location.
Fifth Instruction- will decrement the counter register over her e is C
Sixth Instruction- Will continuously Jump if no zero.
Seventh Instruction- Will Halt the program
Example 2 Write a program on Bubble Sort Instruction Start: L;I B, OFF5H MVI D, 00H MVI C,04H Check: Mov A,M I1; H CMP M JC 1xtbt DC; H MOV M,A DC; H MOV B,M I1; H MVI D,01H 1xtbt: DCR C J1= Check Mov A,D RRC JC Start HLT munotes.in

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The above program will compare two numbers and sort the number in ascending
order
Example 3 To find the largest number in an array of data using 8085 instruction set
Algorithm
1. Load the address of the first element of the array in HL pair
2. Move the count to B register
3. Increment the pointer
4. Get the first data in A register
5. Decrement the counter
6. Increment the pointer
7. Compare the content of memory addressed by HL pair with that of A register
8. If carry 0, go to step 10 or if carry 1 go to step 9
9. Move the content of memory addressed by HL to A register
10. Decrement the counter
11. Check for =ero of the counter. If =F 0, go to step 6, or if = F 1 go to next
step
12. Store the largest data in memory
13. Terminate the Program Instruction Explanation L;I H,4200 Set pointer for array MOV B,M Load the Count LOOP: I1; H Increment the Memory location CMP M If A register ! M go to Head J1C AHEAD Jump to AHEAD label if carry 0 MOV A,M Set new value as largest AHEAD:DCR B Decrement the B counter J1= LOOP Repeat comparisons till count 0 STA 4300 Store the largest value at 4300 HLT Terminate the program munotes.in

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Input 05(4200)
0A(4201)
F1(4202)
1F(4203)
26(4204)
FE(4205)
Output FE(4300)
Example 5 To find the smallest num ber in an array of data using 8085 instruction
set
Algorithm
1. Load the address of the first element of the array in HL pair
2. Move the counttoB –reg.
3. Incrementthe pointer
4. Getthe firstdata inA –reg.
5. Decrementthe count.
6. Incrementthepointer
7. Compare the contentofmemory addressed by HLpairwiththatofA -reg .
8. Ifcarry 1,go tostep10orifCarry 0goto step9
9. Move the contentofmemory addressedby HLtoA –reg.
10. Decrementthecount
11. Checkfor=ero ofthe count. If=F 0, goto step6,orif=F 1go to next step.
12. Storethe smallestdata inmemory.
13. Terminatetheprogram.
Program L;IMOV I1; H,4200B,M H Set pointer for array Loadthe Count MOV A,M Set1stelementaslargestdata DCR B Decrement the count LOOP: I1; H CMP M IfA-reg  Mgo toAHEAD JC AHEAD Jump if carry 1 to AHEAD Label munotes.in

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Input: 05(4200) Array Size
0A(4201)
F1(4202)
1F(4203)
26(4204)
FE(4205)
Output: 0A(4300)
Example 6 To write a program to arrange anarray of descending order
Algorithm
1. Initialize HL pairas memory pointer
2. Get the countat4200intoC –register
3. Copy it in D –register(for bubble sort(1-1)times required)
4. Get the first value in A –register
5. Compare it with the value at next location.
6. If they are out of order, exchange the contents of A –register and Memory
7. Decrement D –register content by 1
8. Repeat steps 5 and 7 till the value in D-register become ze ro
9. Decrement C –register content by 1
10. Repeat steps 3 to 9 till the value in C –register becomes zero REPEAT: L;IMOVD
CR MOV H,4200C,M C
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158MICROPROCESSOR ARCHITECTURE MOV B,M MOV M,A DC; H MOV M,B I1; H SKIP: DCR D J1= LOOP DCR C J1= REPEAT HLT Input: 4200 05 (Array Size) 4201 01 4202 02 4203 03 4204 04 4205 05 Output: 4200 05 (ArraySize) 4201 05 4202 04 4203 03 4204 02 4205 01 7.4 Additional Data Transfer and 16-Bit Arithmetic Instructions
1. Load Register Pair Immediate- L;I Reg pair, 16-bit data. Th e instruction
loads 16 bit data in the register pair designated in the operan d. Eg L;I
H,2034H.
2. Load H and L registers direct-LHLD 16-bit address. The instr uction copies
the contents of the memory location pointed out by the 16-bit a ddress in to
register L and Copies the contents of the next memory location in to register
H. The contents of source memory locations are not altered. Eg LHLD 2040
H.
3. Mov R.M-R.M copies data byte from memory to register. Memor y location,
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159Chapter 7: Programming Techniques w-ith Additional Instructions
4. LDA; B/D Register pair- The c ontents of the designated regis ter pair point
to a memory location. This location in to the accumulator. The contents of
either the register pair or the memory location are not altered . Eg LDA; B
5. Load Accumulator- LDA 16-bit address , the contents of a me mory location,
specified by a 16-bit address in the operand, are copied to the accumulator.
The contents of the source are not altered. Eg LDA 2034H
6. MOV M,R-This instruction copies the contents of the source. T h e s o u r c e
register are not altered. As one of the operands is a memory lo cation, its
location is specified by the contents of the HL registers. Eg M OV M,B
7. STA 16-bit address- The contents of the accumulator are cop ied in to the
memory location specified by the operand. This is a 3-byte inst ruction, the
second byte specifies the low-order address and the third byte. Eg MOV M,B
8. Store Accumulator Indirect- STA; register pair the contents of the
accumulator are copied in to the memory location specified by t he contents
of the operand(register pair). The contents of the accumulator are not altered.
Eg STA; B
9. Store H and L registers indirect- SHLD 16-bit address, the contents of register
L are stored in to the memory location specified by the 16-bit address in the
operand and the contents of the H register are stored in to the next memory
location by incrementing the operand. The contents of register HL are not
altered. This is a 3 byte instruction, the second byte specifie s the low-order
address and the third byte specifies the high-order address. Eg SHLD 2470H
10. Increment register pair by 1-I1; R, the contents of the de signated register
pair are incremented by 1 and t he result is stored in the same place.
Eg I1; H
11. Decrement register pair by 1- DC; R, the contents of the d esignated register
pair are decremented by 1 and the r esult is stored in the same place.
Eg DC; H
12. Add memory(ADD M)- The contents of the operand (memory) ar e added to
the contents of the accumulator and the result is stored in the accumulator.
The operand is a memory location, its location is specified by the contents of
the HL registers. All flags are modified to reflect the result of the addition.
13. Substract Memory (SUB M)- The contents of the operand (mem ory) are
substracted to the contents of the accumulator and the result i s stored in the
accumulator. The operand is a memory location, its location is specified by
the contents of the HL registers. All flags are modified to ref lect the result of
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14. Increment memory by 1/ Decrement memory by 1(I1R M/DCR M) - The
contents of the memory are incremented by 1 using I1R and decre mented by
1 using DCR and the result is stored in the same place. The ope rand is a
memory location, its location is specified by the contents of t he HL registers.
Eg Toperformadditionoftwo8bitnumbersusing8085.
Algorithm
1. Start the program by loading the first data into Accumulator .
2. Move the data to a register (B register).
3. Get the second data and load into Accumulator.
4. Add the two register contents.
5. Check for carry.
6. Store the value of sum and carry in memory location.
7. Terminate the program.
Program

Eg 2 Toper form the subtraction of two 8bit numbers using 8085.



MVI C, 00 InitializeC registerto00 LDA 4150 Loadthevalue toAccumulator. MOV B,A Movethe contentofAccumulatortoBregister. LDA 4151 Loadthevalue toAccumulator. ADD B Addthe value ofregisterBto A J1C LOOP Jumponno carry. I1R C Incrementvalue ofregisterC LOOP:STA 4152 StorethevalueofAccumulator(SUM). MOV A, C Move contentofregisterC toAcc. STA 4153 Storethevalue ofAccumulator(CARR<) HLT Haltthe program. Input: 80(4150) 80(4251) Output: 00(4152) 01(4153) munotes.in

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161Chapter 7: Programming Techniques w-ith Additional Instructions
Algorithm
1. Start the program by loading the first data into Accumulato r.
2. Move the data to a register(B register).
3. Get the second data and load in to Accumulator.
4. Subtract the two register contents.
5. Check for carry.
6. If carry is present take 2’s complement of Accumulator.
7. Store the value of borrow in memory location.
8. Store the difference value (present in Accumulator) to a me mory
9. location and terminate the program.
Program

Input: 06(4150)
02(4251)
Output: 04(4152)
01(4153)MVI C, 00 Initialize C to 00 LDA 4150 Loadthe value to Acc. MOV B,A Move the contentof Acc to Bregister. LDA 4151 Loadthe value to Acc. SUB B J1C LOOP Jumpon no carry. CMA Complement Accumulator contents. I1R A Increment value in Accumulator. I1R C Increment value in register C LOOP:STA 4152 Storethe value of A-reg to memory address. MOV A, C Move contents of register C to Accumulator. STA 4153 Storethe value of Accumulator memory address. HLT Terminate the program. munotes.in

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162MICROPROCESSOR ARCHITECTURE
Toper form the multiplication of two 8 bit numbers using 8085.
ALGORITHM:
1. Start the program by loading HL register pair with address of memory
location.
2. Move the data to a register (B register).
3. Get the second data and load in to Accumulator.
4. Add the two register contents.
5. Check for carry.
6. Increment the value of carry.
7. Check whether repeated addition is over and store the value of product and
carry in memory location.
8. Terminate the program. PROGRAM: MVI D,00 InitializeregisterDto00 MVI A, 00 InitializeAccumulatorcontentto00 L;I H,4150 MOV B,M Get the first number in B-reg I1; H MOV C, M Get the second number in C-reg. LOOP: ADD B Add content of A- reg to register B. J1C 1E;T Jump on no carry to 1E;T. I1R D Increment content of register D 1E;T: DCR C Decrement content of register C. J1= LOOP Jump on no zero to address STA 4152 Store the result in Memory MOV A, D STA 4153 Store the MSB of result in Memory HLT Terminate the program. munotes.in

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163Chapter 7: Programming Techniques w-ith Additional Instructions
Eg 4 Toper form the division of two 8bit numbers using 8085.
Algorithm:
1. Start the program by loading HL register pair with address of memory
location.
2. Move the data to a register (B register).
3. Get the second data and load in to Accumulator.
4. Compare the two numbers to check for carry.
5. Subtract the two numbers.
6. Increment the value of carry .
7. Check whether repeated subtraction is over and store the va lue of product
and carry in memory location.
8. Terminate the program.
Input: FF(4150)
F F ( 4 2 5 1 )
Output: 01(4152) Remainder
F E ( 4 1 5 3 ) 4 u o t i e n tPROGRAM: L;I H,4150 MOV B,M Getthedividendin B – reg. MVI C, 00 ClearC –regforqoutient I1; H MOV A, M Getthe divisorin A –reg. 1E;T: CMP B CompareA -regwithregisterB. JC LOOP Jumponcarry toLOOP SUB B SubtractA –regfromB-reg. I1R C IncrementcontentofregisterC. JMP 1E;T Jumpto1E;T LOOP: STA 4152 Storethe remainderinMemory MOV A, C STA 4153 Storethe quotientinmemory HLT Terminatetheprogram. munotes.in

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164MICROPROCESSOR ARCHITECTURE
7.5 Logic Operations: Rotate,Logics Operations: Compare,
Dynamic Debugging
1. Logic instructions of a microprocessor are simply the instr uctions that carry
out basic logical operations such as OR, AND, XOR and So on. In intel’s
8085 microprocessor, the destination operand for the instructio ns is always
the accumulator register. Here, the logical operations work on a bitwise level.
The corresponding result is also s tored in the accumulator regi ster.
2. Following is the table showing the list of logical instruct ion Sr.
No OP
Code Operand Destination E[planatio
n 1 A1A R A A A1D R A1A B 2 A1A M A A A1D MC (Memory Content) A1A 2050 3 A1I 8-bit Data A A A1D 8-bit data A1I 50 4 ORA R A A OR R ORA B 5 ORA M A A OR MC ORA 2050 6 ORI 8-bit data A A OR 8-bit data ORI 50 7 ;RA R A A ;OR R ;RA B 8 ;RA M A A ;OR MC ;RA 2050 9 ;RI 8 bit data A A ;OR 8-bit data ;RI 50 10 CMA 1one A=1’s CMA 11 CMP R Compares R with A and triggers CMP B 12 CMP M Compares MC with A and triggers the
flag register CMP 2050 13 CPI 8-bit data Compares 8-bit data with A and
triggers the flag register CPI 50 14 RRC none Rotate accumulator right without
carry RRC 15 RLC 1one Rotate accumulator left without carry RLC 16 RAR none Rotate accumulator right with carry RAR 17 RAL none Rotate accumulator left with carry RAL 18 CMC none Compliments the carry flag CMC 19 STC none Sets the carry flag STC munotes.in

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165Chapter 7: Programming Techniques w-ith Additional Instructions
3. Debugging is the process of identifying and removing bug fro m software or
program. It refers to identification of errors in the program l ogic, machine
codes and execution. It gives s tep by step information about th e execution of
code to identify the fault in the program.
3.1 Debugging of Machine code-Translating the assembly languag e to
machine code is similar to building a circuit from a schematic diagram.
Debugging can help in determining
3.1.1 Value of register
3.1.2 Flow of Program
3.1.3 Entry and exit point of a function
3.1.4 Entry in to if or else statement
31.5 Logging of code
3.1.6 Calculation check
3 . 2 C o m m o n S o u r c e s o f E r r o r
1 . S e l e c t i n g a w r o n g c o d e
2. Forgetting second or third byte of instruction
3. Specifying wrong jump locations
4. 1ot reversing the order of high and low bytes in a jump
instruction
5. Writing memory addresses in decimal instead of hexadecima l
6 . F a i l u r e t o c l e a r a c c u m u l a t o r w h e n a d d i n g t w o n u m b e r s
7 . F a i l u r e t o c l e a r c a r r y r e g i s t e r s
8 . F a i l u r e t o s e t f l a g b e f o r e j u m p i n s t r u c t i o n
9. Specifying wrong memory address on Jump instruction
1 0 . U s e o f i m p r o p e r c o m b i n a t i o n o f r o t a t e i n s t r u c t i o n s
3 . 3 T h e d e b u g g i n g p r o c e s s i s d i v i d e d i n t o t w o p a r t s
1 Static Debugging- It is similar to visual inspection of circ uit
board, it is done by a paper and pencil to check the flow chart and
machine codes. It is used to the understanding of code logic an d
structure of program
2. Dynamic Debugging- It involves observing the contents of
register or output after execution of each instruction (in sing le
step technique) or a group of instructions(in breakpoint
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166MICROPROCESSOR ARCHITECTURE
3.4 In single board microprocessor, techniques and tools commo nly used
in dynamic debugging are-
1. Single Step- This technique allows to execute one instructio n at
a time and observe the results of each instruction. Generally, this
is build using hard-wired logic circuit. As we press the single step
run key we will be able to observe the contents of register and
memory location. However, if there is large loop then single st ep
debugging can be very tiring and time-consuming. So instead of
running the loop n times, we can reduce the number of iteration
to check the effectiveness of the loop. The single step techniq ue
is very useful for short programs. This helps to spot: A)incorr ect
addresses B)incorrect jump location in loops C)incorrect data o r
missing codes.
2. Break Point- The breakpoint facility is usually a software routine
that allows users to execute a program in sections. The
breakpoints can be set using RST instruction. When we push the
Execute key, the program will be executed till the breakpoint.
The registers can be examined for the expected result. With the
breakpoint facility, isolate the segment of program with errors .
Then that segment can be debugged using the single-step facilit y.
It is usually used to check : a) Timing loop b) I/O section
c) Interrupts
3. Register Examine- The regist er examine key allows you to
examine the contents of the microprocessor register. This
technique is used in conjunction with either single-step or
breakpoint facility.
Miscellaneous 4uestions
41. Write down some arithmetic Instruction with illustrative program
42. Write Logical instructions with program
43. Describe the concept about dynamic debugging
44. Describe the types of dynamic debugging

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UNIT 3
8
COUNTER TIME DELAYS
Unit Structure
8.1 Objectives
8.2 Introduction
8.3 Counters and Time Delays, Illustrative Program: Hexadecima l Counter
8.4 Illustrative Program: zero-to-nine (Modulo Ten) Counter
8.5 Generating Pulse Waveforms
8.6 Debugging Counter and Time-Delay Programs
8.1 Objectives
At the end of this chapter, the student will be able to
z Describe about Counter and Delays
z Write the program Hexadecimal counter
z Write the program for modulo ten counter
z Illustrate the concept of Pulse waveform
z Elaborate on concept of debugging and Time-Delay Programs
8.2 Introduction
1. The delay will be used in different places to simulate cloc ks, or counters or
some other area.
2. When the delay subroutine is executed, the microprocessor d oes not execute
other tasks. For the delay we are using the instruction executi on times,
executing some instructions in a loop, the delay is generated.
3. So in this chapter we are going to study more about counter s, time delays and
various other programs of 8085 for hexadecimal counter, modulo ten counter,
pulse wave form.
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8.3 Counters and Time Delays, Illustrative Program: He[adecimal
Counter
1. Counters are used to keep track of events
2. Time delays are important in setting up reasonably accurate timing between
two events
3. A Counter is designed simply by loading an appropriate numbe r in to one of
the registers and using the I1R(Increment by one) or the DCR(De crement by
one) instructions. A loop is e stablished to update the count an d each count is
checked to determine whether it has reached the final number, i f not, the loop
is repeated.

Fig. 1 Flow chart of Counter
4. Time Delays- The procedure used to design a specific del ay is similar to that
used to set up a counter. A register is loaded with a number, d epending on
the time delay is required, and then the register is decremente d until it
reaches zero by setting up a loop with a conditional jump instr uction. The
loop causes the delay, depending upon the clock period of the s ystem

Fig 2 Flow chart of Time Delay
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169Chapter 8: Counter & Time Delays
5. Calculating Time Delays- Each instruction passes through di fferent
combinations of opcode fetch, memory read and memory write cycl es
6. Knowing the combination of cycles, one can calculate how long s u c h a n
instruction would require to complete with respect to number of bytes,
number of machine cycles, number of T-State.
7. Knowing how many T-States an instruction requires and keepin g in mind that
a T-State is one clock cycle long, we can calculate the time de lay using the
following formula:
Time Delay No of T-States Clock Period
8. For example - MVI instruction uses 7 T States. Therefore, if the
microprocessor is running at 2 MH=, the instruction would requi re 3.5
microsecond to complete.
9. We can design time delay using following three techniques
9.1 Using One Register
9.2 Using a Register Pair
9.3 Using a Loop with in a Loop
10 Using One Register- A Count is loaded in a register, and we can use a loop
to produce a certain amount of time delay in a program.
10.1 The following is an example of a delay using one register
MVI C, FFH 7T States
LOOP DCR C 4 T States
J1= LOOP 10 T States
The first instruction initializes the loop counter and is exec uted only once
requiring only 7T-States
The following two instructions form a loop that requires 14T S tates to
execute and is repeated 255 times until C becomes 0.
10.2 We need to keep in mind though that in the last iteration of the loop,
the J1= instruction will fail and require only 7T States rather than the
10.
10.3 Therefore,we must deduct 3 T states from the total delay t o get an
accurate delay calculation. To calculate the delay, we use the following
formula
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Whereas Tdelay Total delay, TO delay outside the loop and
TL delay of the loop
TO is the sum of all delays outside the loop and TL is calculat ed using
the formula
TL T Loop T-States 1(1o of iterations)
10.4 Using a single register, one can repeat a loop for a maxi mum count of
255 times.
10.5 It is possible to increase this count by using a register pair for the loop
counter instead of the single register.
10.5 A minor problem arises in how to test for the final count since DC;
and I1; do not modify the flags.
10.6 However, if the loop is looking for when the count become s zero, we
can use a small trick by oring the two registers in the pair an d then
checking the zero flag
11 Using a Register Pair- The Following is an example of a dela y loop set up
with a register pair as the loop counter.
L;I B, 1000H 10T States
LOOP DC; B 6T States
MOV A,C 4 T states
ORA B 4 T Sates
J1= LOOP 10 T States
11.1 Using the same formula from before, we can calculate To 1 0 T
Sates(The delay for the L;I instruction)
TL (24 4096)-3 98301 T States
(24 T-States for the 4 instructions in the loop repeated 4096
times(1000 16 4096 10) reduced by the 3 T sates for the J1= in the last
iteration).
TDelay (10 98301) 0.5 m sec 49.155 msec
12 Using a Loop with in a loop- 1ested loops can be easily set up in assembly
language by using two registers for the two loop counters and u pdating the
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171Chapter 8: Counter & Time Delays

Fig 3 Flow chart for time delay with two loops
12.1 Instead (or in conjunction with) Register Pairs, anested loop structure
can be used to increase thetotal delay produced.
MVI B, 10H 7 T-States
LOOP2 MVI C, FFH 7 T-States
LOOP1 DCR C 4 T-States
J1= LOOP1 10 T-States
DCR B 4 T-States
J1= LOOP2 10 T-States
12.2 The Calculation remains the same except that the formula must be
applied recursively to each loop, Start with the inner loop, th en plug
that delay in the calculation of the outer loop.
12.3 Delay of inner loop
TO1 7 T States (MVI C, FFH)
TL1 (255 14)-3 3567 T States(14 T States for the DCR C and J1=
instructions repeated 255 times (FF 16 255 10 ) minus 3 for the final J1=)
TLoop1 73567 3574 T States
Delay of the outer loop
TO2 7 T States
(MVI B, 10H)
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172MICROPROCESSOR ARCHITECTURE
TL1 (16 (143574))-3 57405 T-States (14 T Sates for the DCR B
and J1= instructions and 3574 T States for loop1 repeated 16 ti mes
minus 3 for the final J1=
T Delay 757405 57412 T Sates
Total Delay(T Delay) 57412 0.5 micro Sec 28.706 Msec
13. Increasing the Time Delay- The Delay can be further increased by using
register pairs for each of the loop counters in the nested loop s set up. It can
also be increased by adding dummy instructions(like 1OP) in the body of the
Loop.

Fig 4 Counter Design with Time Delay


Fig 5 Variations of Counter Flow chart

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173Chapter 8: Counter & Time Delays
14 Illustrative Program on Hexadecimal Counter
Write a program to count continuously in hexadecimal from ffh to 00h in a
system with a 0.5 micro sec clock period. Use register c to set u p a o n e
millisecond delay between each count and display the numbers at one of the
Output ports.
14.1 This Problem has two parts, the first is to set up a cont inuous down-
counter and the second is to design a given delay between two c ounts.
The hexadecimal counter is set up by loading a register with an
appropriate starting number and decrementing it until it become s zero.
After zero count, the register g oes back to FF because decremen ting
zero results in a (- 1), which is FF in 2’s Complement. The 1 ms delay
between each count is set up by using delay techniques. MVI B,00H Store the 00 H in B register and
initialize a counter 1E;T: DCR B Decrement the B counter MVI C, COU1T Load register C with Delay count DELA<: J1= DELA< MOV A,B Copy the Contents of B to A OUT PORT (number of port) Display the output at port JMP 1E;T

Fig 6 Flow chart for He[adecimal Counter
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Time Delay Calculation - Delay loop includes two instructions: DCR C andJ1=
with 14 T-states. Therefore the time delay TL inthe loop (witho ut accounting for
the fact that J1=requires 7 T-States in the last cycle, because countwill remain
same even if the calculations take intoaccount the difference o f 3 T-States) is:
TL 14 T-states ; T (Clock period) ; Count
14 ; (0.5 x 10-6) x Count
(7.0 ; 10-6) ; Count
The Delay outside the loop includes the following instructions:
DCR B 4T Delay outside the loop:
MVI C,COU1T 7T To 35 T-States T
MOV A,B 4T 35 (0.5 10-6)
OUT PORT 10T = 17.5 μs
JMP 10T
35 T-States
Total Time Delay TD To  TL
1ms 17.5 10-6  (7.0 10-6) Count
Count 1x 10-3 ̽ 17.5 x 10-6 Ү14010 ms
7.0 x 10-6
Hence, a delay count 8CH(14010) must be loaded in C.
8.4 Illustrative Program: =ero -to-Nine (Modulo Ten) Counter
Write A Program To Count From0-9 With A One-Second DelayBetween Each
Count. At Count Of9, The Counter Should ResetItself To 0 And Re peat The
Sequence Continuously. UseRegister Pair Hl To Set Up TheDelay, And Display
Each Count AtOne Of The Output Ports. AssumeThe Clock Frequency O f
TheMicrocomputer Is 1 Mhz. START: MVI B,OOH 7 T(no of states) Initialize the B as a counter MOV A,B 4 T Copy the contents of B to A DISPLA<: OUT PORT  10 T Output will be displayed at
particular port L;I H, 16 bit 10 T Load 16 bit data in H and L
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175Chapter 8: Counter & Time Delays MOV A,L 4T Copy the contents of L to A ORA H 4T Oring the data of H J1= LOOP 10/7 Jump if no zero I1R B 4 Increment the B counter CPI 0AH 7 Compare the data J1= DISPLA< 10/7 J= START 10/7

Fig 6 Flow chart Modulo Ten Counter
Time Delay Calculation- The major delay between two counts is p rovided by the
16-bit number in the delay register HL(inner loop in flow chart ). This delay is set
up by using a register pair.
Loop Delay TL 24 T-states T Count
1 second 24 1.0 10-6 Count
Count 1 41666 A2C2H
24 x 10-6
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176MICROPROCESSOR ARCHITECTURE
A2C2H would provide approx 1 sec delay between two counts. To a chieve higher
accuracy in the delay, the instructions outside the loop must b e accounted for delay
calculation. (will be 41665).
8.5 Generating pulse Wave forms
Write A Program To Generate A Continuous Square Wave With the P eriod Of
500Micro Sec. Assume The System Clock Period is 325 1s, And Use Bit D0 To
Output The Square Wave. MVI D,AA 7T Move immediate AA data to D
register ROTATE: MOV A,D 4T Copy the data of accumulator to
register RLC 4T Rotate left with Carry MOV D,A 4T Move the content from A to D A1I 01H 7T And the contents of A register with
01 H OUT PORT 1 10 T Display the output at port 1 MVI B, COU1T Keep the count in B DELA<: DCR B 4T Decrement B J1= DELA< 10/7T JMP ROTATE 10T
A 1 0 1 0 1 0 1 0
After RLC 0 1 0 1 0 1 0 1
A A1D 01H 0 0 0 0 0 0 0 1
COU1T 52.410 34H
8.6 Debugging Counter a nd Time-Delay Programs
1. Errors in counting T-States in a delay loop. Typically, the firstinstruction –
to load a delay register – is mistakenly includedin the loop.
2. Errors in recognizing how many times a loop is repeated.
3. Failure to convert a delay count from a decimal number intoi ts hexadecimal
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177Chapter 8: Counter & Time Delays
4. Conversion error in converting a delay count from decimal to hexadecimal
number or vice versa.
5. Specifying a wrong jump location.
6. Failure to set a flag, especially with 16-bitdecrement/incre ment instructions.
7. Using a wrong jump instruction.
8. Failure to display either the first or the last count.
9. Failure to provide a delay between the last and the last-bu t one count.
Miscellaneous 4uestions
41. Write in short about Counter & Time Delays in 8085
42. Write a program for hexadecimal counter
43. How to calculate time delay for a particular program
44. Write a Program for Modulo ten counter
45. How to write a program for generating pulse wave form
46. Write the steps for debugg ing counter and Timer delay pro grams


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UNIT 3

STACKS AND SUB-ROUTINES
Unit Structure
9.1 Objectives
9.2 Introduction
9.3 Stack, Subroutine, Restart, Condi tional Call, Return Instr uctions
9.4 Advanced Subroutine concepts
.1 Objectives
At the end of this unit, the student will be able to
x Describe the concept of stack and its instruction
x Illustrate more about subroutines
.2 Introduction
1. The stack is an area of memory identified by the programmer for temporary
storage of information.
2. The stack is a LIFO (Last In First Out. ) structure.
3. The stack normally grows backwards into memory.
4. In other words, the programmer defines the bottom of the st ack and the stack
grows up into reducing address range.

Fig 1 Stack Structure
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179Chapter 9: Stacks and Sub-Routines
5. Given that the stack grows backwards into memory, it is cu stomary to place
the bottom of the stack at the end of memory to keep it as far away from user
programs as possible.In the 8085, the stack is defined by setti ng the SP (Stack
Pointer) register.
L;I SP, FFFFH
This sets the Stack Pointer to location FFFFH (end of memory fo r the 8085).
6. Saving Information on the Stack
1. Information is saved on the stack by Pushing it on.
2. It is retrieved from the stack by Poping it off.
3. The 8085 provides two instructions: PUSH and POP for storing
information on the stack and retrieving it back.
4. Both PUSH and POP work w ith register pairs O1L<.
7. The PUSH Instruction
PUSH B/D/H/PSW
Decrement SP
Copy the contents of register B to the memory location pointed to by SP
Decrement SP
Copy the contents of register C to the memory location pointed to by SP

Fig 2. Push Operation of Stack
8. The POP Instruction
P O P B / D / H / P S W
Copy the contents of the memory location pointed to by the SP to register E
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180MICROPROCESSOR ARCHITECTURE
I n c r e m e n t S P
Copy the contents of the memory location pointed to by the SP to register D
I n c r e m e n t S P

Fig.3 - POP operation on Stack
9. Operation of the Stack
1. During pushing, the stack operates in a “decrement then store”
style.The stack pointer is decremented first, then the informat ion is
placed on the stack.During poping, the stack operates in a “use then
increment” style.The information is retrieved from the top of the the
stack and then the pointer is in cremented.The SP pointer always points
to “the top of the stack”.
2. LIFO
T h e o r d e r o f P U S H s a n d P O P s m u s t b e o p p o s i t e o f e a c h o t h e r i n order
to retrieve information back into its original location.
PUSH B
PUSH D
...
POP D
POP B
R e v e r s i n g t h e o r d e r o f t h e P O P i n s t r u c t i o n s w i l l r e s u l t i n t h e exchange
of the contents of BC and DE.
3. The PSW Register Pair
The 8085 recognizes one additional register pair called the PS W
(Program Status Word).This register pair is made up of the
Accumulator and the Flags registers.It is possible to push the PSW onto
the stack, do whatever operations are needed, then POP it off o f the
stack.The result is that the contents of the Accumulator and th e status
of the Flags are returned to what they were before the operatio ns were
executed.
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181Chapter 9: Stacks and Sub-Routines
4. Cautions with PUSH and POP
PUSH and POP should be used in opposite order.There has to be as
many POP’s as there are PUSH’s.If not, the RET statement will pick
up the wrong information from the top of the stack andthe progr am will
fail.It is not advisable to place PUSH or POP inside a loop.
5. Program to Reset and display Flags
C l e a r a l l F l a g s .
L o a d 0 0 H i n t h e a c c u m u l a t o r , a n d d e monstrate that the zero fla g is not
affected by data transfer instruction.
L o g i c a l l y O R t h e a c c u m u l a t o r w i t h i t s e l f t o s e t t h e = e r o f l a g , and
display the flag at PORT1 or store all flags on the stack.
6. Program to Reset and display Flags
;;00 L;I SP,;;99H Initialize the stack
03 MVI L,00H Clear L
05 PUSH H Place (L) on stack
06 POP PSW Clear Flags
07 MVI A, 00H Load 00H
09 PUSH PSW Save Flags on stack
0A POP H Retrieve flags in L
0B MOV A, L
0C OUT PORT0 Display Flags (00H)
0E MVI A, 00H Load 00H Again

7. Program to Reset and display Flags
;;10 ORA A Set Flags and reset(C<, AC)
11 PUSH PSW Save Flags on Stack
12 POP H Retrieve Flags in L
13 MOV A, L
14 A1I 40H Mask all Flags except =
16 OUT PORT1 Displays 40H
18 HLT End of Program

Fig. 4 - Flags affected after e[ecuting above program
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182MICROPROCESSOR ARCHITECTURE
.3 Stack, Subroutine, Restart, C onditional Call, Return Instru ctions
1. Subroutines
1. A subroutine is a group of instructions that will be used re peatedly in
different locations of the program.
2. Rather than repeat the same instructions several times, they can be
grouped into a subroutine that iscalled from the different loca tions.
3. In Assembly language, a subroutine can exist anywhere in the code.
4. However, it is customary to place subroutines separately fr om the main
program.
5. The 8085 has two instructions for dealing with subroutines.
6. The CALL instruction is used to redirect program execution to the
subroutine.
7. The RTE instruction is used to return the execution to the calling
routine.
2. The CALL Instruction
1. CALL 4000H
1 . 1 3 - b y t e i n s t r u c t i o n .
1.2 Push the address of the instruction immediately following
theCALL onto the stack and decremen t the stack pointer register
by two.Load the program counter with the 16-bit address
supplied with the CALL instruction.
1.3 Jump Unconditionally to memory location.

Fig 5 CALL Instruction
2. MP reads the subroutine address from the next two memory l ocation
and stores the higher order 8 bit of the address in the W regis ter and
stores the lower order 8 bit of the address in the = register.
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183Chapter 9: Stacks and Sub-Routines
3. PUSH the address of the instruction immediately following the CALL
on to the stack (Return address).
4. Loads the program counter with the 16-bit address supplied with the
CALL instruction from W= register.
3. The RTE Instruction
1. It is 1-byte instruction
2. Retrieve the return address from the top of the stack and i ncrements
stack pointer register by two.
3. Load the program counter with the return address.
4. Unconditionally returns from a subroutine.

Fig. 6 - RTE Instruction
4. Illustrates the e[change of i nformation between stack an d Program
Counter

Fig. 7 - Program
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Program E[ecution

Fig. 8 - Program e[ecution with CALL instruction
5. CALL E[ecution
Instruction requires five machine cycles and eighteen Tstates: Call instruction
is fetched, 16-bit address is read during M2 and M3 and stored temporarily
in W/=registers. In next two cycles content of program counter are stored on
the stack (address from where microprocessor continue it execut ion of
program after completion of the subroutine)

Fig.  - Data transfer during e[ecution of CALL instruction
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185Chapter 9: Stacks and Sub-Routines
6. RET E[ecution
P r o g r a m e x e c u t i o n s e q u e n c e i s t r a n s f e r r e d t o t h e m e m o r y l o c a t i on 2043H
location.M1 is normal fetch cycle during M2 contents of stack p ointer are
placed on address bus so 43H data is fetched and stored on = re gister and SP
is upgraded.Similarly for M3. Program sequence is transfered to 2043H by
placing contents of memory and stack

Fig. 10 - Data transfer during e[ecution of RET instruction
7. Passing Data to a Subroutine
1. In Assembly Language data is passed to a subroutine through registers.
2. The data is stored in one of the registers by the calling pr ogram and the
subroutine uses the value from the register.
3. The other possibility is to use agreed upon memory locations .
4. The calling program stores the data in the memory location a nd the
subroutine retrieves the data from the location and uses it.
8. Restart, Conditional Call Return Instructions
1. In addition to unconditional CALL and RET instructions, the 8085
instruction set includes eight restart instructions and eight c onditional
CALL and Return instructions.
2. RST Instruction
2 . 1 R S T i n s t r u c t i o n a r e 1 - b y t e c a l l i n s t r u c t i o n s t h a t t r a n s f e r the
program execution to a specific location on page 00H
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186MICROPROCESSOR ARCHITECTURE
2 . 2 E x e c u t e d t h e s a m e w a y a s c a l l i n s t r u c t i o n s , t h e 8 0 8 5 s t o r es the
contents of the program counter(the address of the next
instruction) on the top of the stack and transfers the program to
the restart location.

Fig. 11 - 7 types of RST
3. The conditional Call and Return instructions are based on fo ur data
conditions(flags): Carry, Sign and Parity. In case of a conditi onal call
the program is transferred to the subroutine if condition is me t. In case
of a conditional return instruction, the sequence returns to th e main
program if the condition is met.

Fig. 12 - Conditional CALL

Fig. 13 - CALL instruction for subroutine
Fig. 14 - Conditional Return Instructions
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187Chapter 9: Stacks and Sub-Routines
.4 Advanced Subroutine Concepts
1. According to Software Engineering practices, a proper subrou tine:Is only
entered with a CALL and exited with an RTE
2. Has a single entry point
3. Do not use a CALL statement to jump into different points o f the same
subroutine.
4. For eg Writing Subroutines
Write a Program that will display FF and 11 repeatedly on the seven segment
display. Write a ‘delay’ subrouti ne and Call it as necessary.
C000: L;I SP, FFFF
C003: MVI A, FF
C005: OUT 00
C007: CALL C014
C00A: MVI A, 11
C00C: OUT 00
C00E: CALL 1420
C011: JMP C003

4.1 Writing Subroutines
DELA<: C014: MVIB, FF
C016: MVIC, FF
C018: DCR C
C019: J1= C018
C01C: DCR B
C01D: J1= C016
C020: RET
5. 1esting Subroutines
1. The Programming technique of a subroutine calling another su broutine.
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Fig. 15 - Nested Subroutines
6. Write a program to provide the given on /off time to th ree traffic lights
(Green, Yellow and Red) and two pe destrian signs(Walk and Don’t Walk).
The signal lights and signs are turned on /off by the data bits of an output port

Fig. 16 - Input to a program

Fig. 17 - Schematic e[ecution of a program

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189Chapter 9: Stacks and Sub-RoutinesLabel Mnemonics Comments L;I SP, 0099H Initalize stack pointer at location 0099H START MVI A, 41H Load accumulator with the bit pattern for green
light and Walk Sign OUT PORT  Turn on Green light and Walk sign, that is
displayed on out port number MVI B,0FH Use B as a counter to count 15 seconds, B is
decremented in the subroutine CALL DELA< Call delay subroutine located at 50H MVI A, 84H Load accumulator with the bit for and Don’t Walk OUT PORT  Turn on Yellow light and Don’t Walk MVI B,05 Set up 5 second delay counter CALL DELA< Call of subroutine MVI A, 90H Load accumulator with the bit pattern of Red
light and Don’t Talk OUT PORT  Turn on Red light, kepp Don’t walk on and turn
off yellow light CALL DELA< JMP START Go back to location START to repeat the
sequence DELA< PUSH D Save the contents of DE and accumulator PUSH PSW Push the contents on program status word SECO1D L;I D, COU1T Load register pair DE with a count for 1 second
delay LOOP DC; D Decrement register pair DE MOV A,D ORA E OR(D) and ( E) to set =ero flag J1= LOOP Jump to loop if delay decrement the counter J1= SECO1D Go back to repeat 1-second delay POP PSW Retrieve contents of saved registers POP D RET Return to main program munotes.in

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190MICROPROCESSOR ARCHITECTURE
Miscellaneous 4uestions
41. Explain the concept of Stack, subroutines, Return, Restar t and conditional
Call
42. Explain about nesting of subroutines
References
To refer opcodes for program in simulator use the link Here
https://electricalvoice.com/ opcodes-8085-microprocessor/

™™™

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UNIT 4
10
CODE CONVERSION WITH BCD
Unit Structure
10.0 Objectives
10.1 Introduction
10.2 BCD –TO- Binary Conversion
1 0 . 2 . 1 I l l u s t r a t i v e P r o g r a m : 2 - D i g i t B C D – to- Binary Conversion
10.3 Binary –TO-BCD Conversion
1 0 . 3 . 1 I l l u s t r a t i v e P r o g r a m : B i n a r y – To-Unpacked-BCD Conversion
10.4 BCD-TO-Seven-Segment-LED Code Conversion
1 0 . 4 . 1 I l l u s t r a t i v e P r o g r a m : B C D - TO-Common-Cathode-LEDCode
Conversion
10.5 Binary –TO-ASCII A1D ASCII –TO-Binary Code Conversion
1 0 . 5 . 1 I l l u s t r a t i v e P r o g r a m : B i n a r y - T o - A S C I I H e x C o d e C o n v e r sion
10.5.2 Illustrative Program: ASCII Hex-to-Binary Conversion
10.6 Summary
4uestions and Programming Assignment s
10.0 Objectives
Write programs and subroutine to
x Convert a packed BCD number (0 -99) into its binary equivalent.
x Convert a binary digit ( 0 to F ) into its ASCII Hex code and vi ce versa.
x Select an appropriate seven-segment code for a given binary num ber using
the table look-up technique.
x Convert a binary digit ( 0 to F ) into its ASCII Hex code and vi ce versa.
x Decimal- adjust 8-bit BCD addition and subtraction.
x Perform such arithmetic operation as multiplication and subtrac tion using 16-
bit data related instructions.
x Demonstrate uses of instructions such as DAD, PCHL, ;THL, and ; CHG.
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192MICROPROCESSOR ARCHITECTURE
10.1 Introduction
In microprocessor applications, various number systems and code s are used to input
data or to display results. The ASCII (American Standard Code f or Information
Interchange) keyboard is a commonly used input device for disk- based
microcomputer systems. Similarly, alphanumeric characters (lett ers and numbers)
are displayed on a CRT( cathode ray tube) terminal using the AS CII code. However
, inside the microprocessor , data processing is usually perfor med in binary. In some
instances, arithmetic operations are performed in BCD numbers. Therefore, data
must be converted from one code to another code. The programmin g techniques
used for code conversion fall into four general categories.
1. Conversion based on position of a digit in a number (BCD to binary and vice
versa) .
2. Conversion based on hardware consideration (binary to seven -segment code
using table look-up procedure).
3. Conversion based on sequential order of digits (binary to A SCII and vice
versa).
4. Decimal adjustment in BCD arithmetic operations. (This is an adjustment
rather than a code conversion).
This chapter discusses these techniques with various examples as
subroutines. The subroutines are written to demonstrate industr ial practices
in writing software, and can be verified on single- board micro computers. In
addition, instructions related to 16- bit data operations are i ntroduced and
illustrated.
10.2 BCD –to- Binary Conversion
In most microprocessor –based products, data are enter ed and displayed in decimal
numbers.
For example, in an instruction laboratory , readings such as vo ltage and current are
maintained in decimal numbers, and data are entered through a d ecimal keyboard.
The system-monitor program of the instrument converts each key into equivalent
4- bit binary number and stores two BCD number in an 8-bit regi ster or a memory
location. These numbers are called packed BCD. Even if data are entered in
decimal digits, it is inefficient to process data in BCD number s because , in each 4-
bit combination, digit A though F are unused. Therefore, BCD nu mbers are
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193Chapter 10: Code Conversion with BCD
The conversion of a BCD number into its binary equivalent emplo ys the principle
of positional weighting in a given number.
For example: 72 10 7 10 2
The digit 7 represents 70, based on its second position from th e right. Therefore ,
converting 72 BCD into its binary equivalent requires multiplying the second dig it by
10 and adding the first digit.
Converting a 2- digit BCD number into its binary equivalent req uires the following
steps:
1. Separate an 8- bit packed BCD number into two 4- bit unpack ed BCD digits:
BCD 1 and BCD 2
2. Convert each digit into its binary value according to its p osition.
3. Add both binary numbers to obtain the binary equivalent of the BCD number.
E[ample 10.1: - Convert 72 BCD into its binary equivalent
72 10 0111 0010 BCD
Step 1 : 0111 0010 0000 0010 Unpacked BCD 1
0000 0111 Unpa cked BCD 2
Step 2 : Multiply BCD 2 by 10 ( 7 10)
Step 3 : Add BCD 1 to the answer in step 2
The multiplication of BCD 2 by 10 can be performed by various methods. One
method is multiplication with repeated addition: add 10 seven t imes. This technique
is illustrated in the next program.
10.2.1 Illustrative Program: 2- Digit BCD – to- Binary Conversion
Problem Statement
A BCD number between 0 and 99 is stored in an R/W memory locati on called the
Input Buffer (I1BUF) . Write a main program and a conversion su broutine
(BCDBI1) to convert the BCD number into its equivalent binary n umber. Store the
result in a memory location defined as the Output Buffer (OUTBU F).
Program START : L;I SP, STACK Initialize stack pointer L;I H, I1BUF Point HL index to the Input Buffer Memory
location where BCD number is stored. L;I B,OUTBUF Point BC index to the Output Buffer memory
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194MICROPROCESSOR ARCHITECTURECALL BCDBI1 Call BCD to binary conversion routine STA; B Store binary number in the Output Buffer HLT End of program
BCDBI1 : Function : This subroutine converts a BCD number into its binary
equivalent
Input : A 2-digit packed BCD number in the accumulator
Output : A binary number in the accumulator
1o other register contents are destroyed.
Example : Assume BCD number is 72.
PUSH B  Save BC registers
PUSH D  Save DE registers A 0111 0010 72 10
MOV B,A  Save BCD number B 0111 0010 72 10
A1I 0FH  Mask most significant four bits A 0000 0010 02 10
MOV C,A  Save unpacked BCD 1 in C C 0000 0010 02 10
MOV A,B  Get BCD again A 0111 0 010 72 10
A1I F0H  Mask least significant four bits A 0111 0000 70 10
RRC : Convert most significant four
RRC bits into unpacked BCD 2
RRC
RRC
MOV D,A Save BCD 2 in D A 0000 0111 07 10
;RA A Clear accumulator D 000 0 0111 07 10
MVI E,0AH  Set E as multiplier of 10 E 0000 10 10 0AH
SUM : ADD E  Add 10 until (D) 0 Add E as many times as (D)
DCR D Reduce BCD 2 by one
J1= SUM  Is multiplication com plete " After adding E seven times A
If not ,go back and add again contains : 01 00 0110
ADD C  Add BCD 1 C 0000 0010
BBBBBBBBBBBBBBBBBBBBBB
A 0100 1000 48H
POP D  retrieve previous contents
RET
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195Chapter 10: Code Conversion with BCD
Program Description
1. In writing assembly language programs, the use of labels is a common
practice. Rather than writing a specific memory location or a p ort number a
programmer uses such labels as I1BUF (Input Buffer) and OUTBUF (Output
Buffer ). Using labels give flexibility and ease of documentati on.
2. The main program initializes the stack pointer and two memo ry indexes. It
brings the BCD number into the accumulator and passes that para meter to the
subroutine.
3. After returning from the subroutine , the main program stor es the binary
equivalent in the Output Buffer memory.
4. The subroutine saves the contents of the BC and DE register s because these
registers are used in the subroutine. Even if this particular m ain program does
not use the DE registers, the subroutine may be called by some other program
in which the DE registers are being used. Therefore, it is good practice to
save the registers that are used in the subroutine, unless para meters are passed
to the subroutine. The accumulator contents are not saved becau se that
information is passed to the subroutine.
5. The conversion from BCD to binary is illustrated in the sub routine with the
example of 72 BCD converted to binary.
Program E[ecution
To execute the program on a single-board computer, complete the following steps:
1. Assign memory addresses to the instructions in the main pro gram and in the
subroutine .Both can be assigned consecutive memory addresses.
2. Define STACK: the stack location with a 16- bit address in the R/W memory
(such as 2099H).
3. Define I1BUF (Input Buffer) and OUTBUF (Output Buffer): two memory
locations in the R/W memory (e.g. 2050H and 2060H).
4. Enter a BCD byte in the Input Buffer (e.g. 2050H).
5. Enter and execute the program.
6. Check the contents of the Output Buffer memory location(206 0H) and verify
the answer.
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196MICROPROCESSOR ARCHITECTURE
10.3 Binarys –to-BCD Conversion
In most microprocessor –based products, numbers are displayed in decimal.
However, if data processing inside the microprocessor is perfor med in binary, it is
necessary to convert the binary results into their equivalent B CD numbers just
before they are displayed. Results are quite often stored in R/ W memory locations
called the Output Buffer .
The conversion of binary to BCD is performed by dividing the nu mber by the
powers of ten the division is performed by the subtraction met hod.
For example, assume the binary number is
1 1 1 1 1 1 1 1 2 (FFH) 255 10
To represent this number in BCD requires twelve bits or three B CD digits, labelled
here as BCD 3 (MSB) , and BCD 1(LSB) 0010 0101 0101 BCD 3 BCD 2 BCD 1 The conversion can be performed as follows :
Step 1 : If the number is less than 100 , go to Step 2 otherwise , di vide by 100 or
subtract 100 repeatedly until the remainder is less than 100.Th e quotient is the most
significant BCD digit , BCD 3
Step 2 : If the number is less than 10 , go to step 3 otherwise divide by 10
repeatedly until the remainder is less than 10. The quotient is BCD 2
Step 3: The remainder from Step 2 is BCD 1 Example 4uotient 255
-100
-100 155
55
BCD 3
1
1
2 55 -10
-10
-10
-10
-10 45
35
25
15
05 1
1
1
1
1 BCD 2 5
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197Chapter 10: Code Conversion with BCD
10.3.1 Illustrative Program: Binary – To-Unpacked-BCD Conversion
Problem Statement
A binary number is stored in memory location BI1BBCD store each BCD as two unpacked BCD digits in the output Bu ffer. To
perform this task, write a main program and two subroutines: on e to supply the
powers of ten and the other to perform the conversion.
Program
This program converts an 8- bit binary number into a BCD number  thus it requires
12 bits to represent three BCD digits. The result is stored as three unpacked BCD
digits in three Output-Buffer memory locations. L;I SP,STACK Intialize stack pointer L;I H, BI1Bstored MOV A,M Transfer byte CALL PWRTE1 call subroutine to load power of 10 HLT PWRTE1:  this subroutine loads the power of 10 in register B and calls the
binary – to- BCD conversion routine.  Input : Binary number in accumulator
Output : Powers of ten and stores BCD1 in the first Output-
Buffer memory
 Calls BI1BCD routine and modifies register B L;I H,OUTBUF Point HL index to Output-Buffer memory MVI B,64H Load 100 in register B CALL BI1BCD  Call conversion MVI B,0AH  Load 10 in register B CALL BI1BCD MOV M,A Store BCD 1 RET BI1BCD  This subroutine coverts a binary number into BCD and stores
BCD2 and BCD 3 in the Output Buffer  Input : Binary number in accumulator and powers of 10 in B
 Output : BCD 2 and BCD 3 in Output Buffer
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198MICROPROCESSOR ARCHITECTURE MVI M,FFH Load buffer with (0-1) 1;TBUF: I1R M  Clear buffer and increment for each
subtraction SUB B  Subtract power of 10 from binary number J1C 1;TBUF  Is number ! power of 10" If yes, add 1 to
buffer memory ADD B  If no , add power of 10 to get back
remainder I1; H Go to next buffer location RET
Program Description
This program illustrates the concepts of the nested subroutine and the multiple-calll
subroutine. The main program calls the PWRTE1 subroutine  in t urn the
PWRTE1 calls the BI1BCD subroutine twice.
1. The main program transfers the byte to be converted to the a ccumulator and
calls the PWRTE1 subroutine.
2. The subroutine PWRTE1 supplies the powers of ten by loading register B
and the address of the first Output-Buffer memory location , an d calls the
conversion routine BI1BCD.
3. In the BI1BCD conversion routine , the Output-Buffer memory is used as a
register. It is incremented for each subtraction loop. This ste p also can be
achieved by using a register in the microprocessor. The BI1BCD subroutine
is called twice, once after loading register B with 64H (100 10 ) and again after
loading register B with 0AH (10 10).
4. During the first call of BI1BCD, the subroutine clears the Output Buffer ,
stores BCD 3, and points the HL registers to the next Output-Buffer locatio n.
The instruction ADD B is necessary to restore the remainder bec ause one
extra subtraction is performed to check the borrow.
5. During the second call of BI1BCD , the subroutine again cle ars the output
buffer, stores BCD 2 , and points to the next buffer location. BCD 3 is already
in the accumulator after the ADD instruction, which is stored i n the third
Output- Buffer memory by the instruction MOV M,A in the PWRTE1
subroutine.
This is an efficient subroutine it combines the functions of storing the answer
and finding a quotient. However, two subroutines are required, and the
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199Chapter 10: Code Conversion with BCD
10.4 BCD-to-Seven-Segment-Led Code Conversion
When a BCD number is to be displayed by a seven-segment LED, it is necessary
to convert the BCD number to its seven-segment code. The code i s determined by
hardware considerations such as common-cathode or common-anode LED the cod
has no direct relationship to binary numbers. Therefore , to di splay a BCD digit at
a seven-segment LED , the table look-up technique is used.
In the look-up technique the codes of the digits to be displaye d are stored
sequentially in memory. The conversion program locates the code of a digit based
on its magnitude and transfers the code to the MPU to send out to a display port.
The table look-up technique is illustrated in the next program.
10.4.1 IllustrativeProgram:BCD-TO-COMMON-CATHODE-LED CODE
CONVERSION
Problem Statement
A set of three packed BCD numbers (six digits) representing tim e and temperature
are stored in memory locations starting at ;;50H. The seven-seg ment codes of the
digit 0 to 9 for a common-cathode LED are stored in memory loca tions starting at
;;70H, and the Output-Buffer memory is reserved at ;;90H.
Write a main program and two subroutines, called U1PAK and LEDC OD , to
unpack the BCD numbers and select an appropriate seven-segment code for each
digit. The codes should be stored in the Output-Buffer memory.
Program L;I SP,STACK  Initialize stack pointer L;I H, ;;50H  Point HL where BCD digits are stored. MVI D,03H  1umber of digits to be converted is placed
in D CALL U1PAK Call subroutine to unpack BCD numbers HLT  End of conversion U1PAK:  This subroutine unpacks the BCD number in two single digits Input : Starting memory address of the packed BCD numbers in
HL registers
1umber of BCDs to be converted in register D
Output : Unpacked BCD into accumulator and output
Buffer address in BC
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200MICROPROCESSOR ARCHITECTURE1;TBCD: MOV A,M Get packed BCD number A1I F0H Masked BCD 1 RRC RRC Rotate four times to place BCD 2 as unpacked
single-digit BCD RRC RRC CALL LEDCOD  Find seven-segment code I1; B Point to next buffer location MOV A,M Get BCD number again A1I 0FH Separate BCD 1 CALL LEDCOD I1; B I1; H  Point to next BCD DCR D  One conversion complete , reduce BCD
count J1= 1;TBCD If all BCDs are not yet converted , go back
to convert next BCD RET LEDCOD:  This subroutine converts an unpacked BCD into its seven-
segment-LED code Input :An unpacked BCD in accumulator
Memory address of the buffer in BC register
Output : Stores seven-segment code in the output buffer PUSH H Save HL contents of the caller L;I H,CODE  Point index to beginning of seven-segment
code ADD L  Add BCD digit to starting address of the
code MOV L,A  Point HL to appropriate code MOV A,M  Get seven- segment code STA; B Store code in buffer POP H RET

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201Chapter 10: Code Conversion with BCDCODE: 3F  Digit 0: Common- cathode codes 06  Digit 1 5B  Digit 2 4F  Digit 3 66  Digit 4 6D  Digit 5 7D  Digit 6 07  Digit 7 7F  Digit 8 6F  Digit 9 00 Invalid Digit
Program Description / Output
1. The main program initializes the stack pointer, the HL regi ster as a pointer
for BCD digits , and the counter for the number off digits the n it calls the
U1PAK subroutine.
2. The U1PAK subroutine transfers a BCD number into the accumu lator and
unpacks it into two BCD digits by using the instruction A1I and RR. This
subroutine also supplies the address of the buffer memory to th e next
subroutine, LEDCOD. The subroutine is repeated until counter D becomes
zero.
3. The LEDCOD subroutine saves the memory address of the BCD n umber and
points the HL register to the beginning address of the code.
4. The instruction ADD L adds the BCD digit in the accumulator to the starting
address of the code. After storing the sum in register L, the H L register points
to the seven-segment code of that BCD digit.
5. The code is transferred to the accumulator and stored in th e buffer.
T h i s i l l u s t r a t i v e p r o g r a m u s e s t h e t e c h n i q u e o f t h e n e s t e d s u b routine (one-
subroutine calling another).
Parameters are passed from one subroutine to another therefor e, we should
be careful in using Push instructions to store register content s on the stack. In
addition , the LEDCOD does not account for a situation if by a dding the
register L a carry is generated.
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10.5 Binary –To-ASCII and ASCII –to-Binary Code Conversion
The American Standard Code for Information Interchange ( known as ASCII) is
used commonly in data communication. It is a seven-bit code, an d its 128( 27 )
combinations are assigned different alphanumeric characters. Fo r example, the
hexadecimal capital letters 30H to 39H represent 0 to 9 ASCII d ecimal numbers.
and 41H to 5AH represent capital letters A though =  in this code , bit D 7 is zero.
In serial data communication, bit D 7 is used for parity checking.
The ASCII keyboard is a standard input device for entering prog rams in a
microcomputer. When an ASCII character is entered, the micropro cessor receives
the binary equivalent of the ASCII Hex number. For example, whe n the ASCII key
for digit 9 is pressed, the microprocessor receives the binary equivalent of 39H,
which must be converted to the binary 1001 for arithmetic opera tions. Similarly, to
display digit 9 at the terminal, the microprocessor must send o ut the ASCII Hex
code (39H) .
These conversions are done through software ,as in the followin g illustrative
program.
10.5.1 Illustrative Program: Binary-To-ASCII He[ Cod Conversion
Problem Statement
An 8-bit binary number (e.g. 9FH) is stored in memory location ;;50H .
1. Write a program to
a . T r a n s f e r t h e b y t e t o t h e a c c u m u l a t o r .
b . S e p a r a t e t h e t w o n i b b l e s .
c . C a l l t h e s u b r o u t i n e t o c o n v e r t e a c h n i b b l e i n t o A S C I I H e x code.
d . S t o r e t h e c o d e s i n m e m o r y l o c a t i o n s ; ; 6 0 H a n d ; ; 6 1 H .
2. Write a subroutine to convert a binary digit ( 0 to F) int o ASCII Hex Code.
Main Program L;I SP,STACK  Initialize the stack pointer L;I H, ;;50H  Point index where binary number is
stored. L;I D,;;60H  Point index where ASCII code is
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203Chapter 10: Code Conversion with BCD RRC RRC
RRC
RRC Shift high-order nibble to the
position of low-order nibble CALL ASCII  Call conversion routine STA; D Store first ASCII Hex in ;;60H I1; D Point to next memory location ,get
ready to store next byte MOV A,B Get number again for second digit. CALL ASCII STA; D HLT ASCII : This subroutine converts a binary digit between 0 to F to
ASCII Hex Code Input : Single binary number 0 to F in the accumulator.
 Output : ASCII Hex code in the accumulator A1I 0FH Mask high-order nibble CPI 0AH Is digit less than 10 10 " JC CODE If digit is less than 10 10 , go to
CODE to add 30H ADI 07H Add 7H to obtain code for digits
from A to F CODE: ADI 30H Add base number 30H RET
Program Description
1. The main program transfers the binary data byte from the me mory locations
to the accumulator.
2. It shifts the high-order nibble into the low-order nibble, calls the conversion
subroutine, and stores the converted value in the memory.
3. It retrieves the byte again and repeats the conversion proc ess for the low-
order nibble.
In this program, the masking instruction A1I is used once in th e subroutine rather
than twice in the main program as illustrated in the program fo r BCD –To –
Common-Cathode Code Conversion.

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10.5.2 Illustrative Program :ASCII He[-to-Binary Conversion
Problem Statement
Write a subroutine to convert an ASCII Hex number into its bina ry equivalent. A
calling program places the ASCII number in the accumulator , an d the subroutine
should pass the conversion to the accumulator.
Subroutine ASCBI1 : This subroutine converts an ASCII Hex number into its binary
equivalent
Input: ASCII Hex number in the accumulator
Output : Binary equivalent in the accumulator SUI 30H  Subtract 0 bias from the number CPI 0AH  Check whether number is between 0 to 9 RC  If yes , return to main program SUI 07H  If not , subtract 07H to find number
between A and F RET
Program Description:
This program subtracts the ASCII weighting digits from the numb er. This process
is exactly opposite to that of the Illustrative Program that co nverted binary into
ASCII Hex .However, this program uses two return instructions , an illustration of
the multiple-ending subroutine.
10.6 Summary
The system-monitor program of the instrument converts each key into equivalent
4- bit binary number and stores two BCD number in an 8-bit regi ster or a memory
location. These numbers are called packed BCD.
Even if data are entered in decimal digits, it is inefficient to process dat a in BCD
numbers because, in each 4- bit combination, digit A though F a re unused.
Therefore, BCD numbers are generally converted into binary numb ers for data
processing.
The conversion of a BCD number into its binary equivalent emplo ys the principle
of positional weighting in a given number.
In most microprocessor –based products, numbers are displayed in decimal.
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205Chapter 10: Code Conversion with BCD
necessary to convert the binary results into their equivalent B CD numbers just
before they are displayed. Results are quite often stored in R/ W memory locations
called the Output Buffer .
The conversion of binary to BCD is performed by dividing the nu mber by the
powers of ten the division is performed by the subtraction met hod.
When a BCD number is to be displayed by a seven-segment LED, it is necessary
to convert the BCD number to its seven-segment code. The code i s determined by
hardware considerations such as common-cathode or common-anode LED the cod
has no direct relationship to binary numbers. Therefore, to dis play a BCD digit at
a seven-segment LED, the table look-up technique is used.
In the look-up technique the codes of the digits to be displaye d are stored
sequentially in memory. The conversion program locates the code of a digit based
on its magnitude and transfers t he code to the MPU to send out to a display port.
The American Standard Code for Information Interchange ( known as ASCII) is
used commonly in data communication. It is a seven-bit code, an d its 128( 27 )
combinations are assigned different alphanumeric characters. Fo r example, the
hexadecimal capital letters 30H to 39H represent 0 to 9 ASCII d ecimal numbers.
and 41H to 5AH represent capital letters A though =  in this code , bit D 7 is zero.
In serial data communication, bit D 7 is used for parity checking.
The ASCII keyboard is a standard input device for entering prog rams in a
microcomputer. When an ASCII character is entered, the micropro cessor receives
the binary equivalent of the ASCII Hex number. For example, whe n the ASCII key
for digit 9 is pressed, the microprocessor receives the binary equivalent of 39H,
which must be converted to the binary 1001 for arithmetic opera tions. Similarly, to
display digit 9 at the terminal, the microprocessor must send o ut the ASCII Hex
code (39H) .
4UESTIONS AND PROGRAMMING ASSIGNMENTS
41) Explain BCD –to –binary conversion with examples.
42) Write a program for 2-digit BCD to binary conversion
43) Explain Binary –to –BCD conversion with examples.
44) Write a program for binary to unpacked BCD conversion.
45) Rewrite the BCDBI1 subroutine to include storing results in the Output
Buffer . Eliminate unnecessary PUSH and POP instructions.
46) Write a program for BCD to c ommon cathode LED code convers ion.
47) Write a program for binary t o ASCII Hex code conversion
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Books and References
1. Computer System Architecture by M. Morris Mano , PHI Public ation, 1998.
2. Structured Computer Organization by Andrew C. Tanenbaum , P HI
Publication.
3. Microprocessors Architecture, Programming and Application w ith 8085 by
Ramesh Gaonker ,PE1RAM , Fifth Edition ,2012.

™™™

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207UNIT 4
11
BCD ARITHMETIC AND 16-BIT
DATA OPERATION
11.0 Objectives
11.1 Introduction
11.2 BCD Addition
1 1 . 2 . 1 I l l u s t r a t i v e P r o g r a m : A d d i t i o n o f U n s i g n e d B C D 1 u m b e r s
11.3 BCD Subtraction
1 1 . 3 . 1 I l l u s t r a t i v e P r o b l e m : S u b t r a c t i o n o f T w o P a c k e d B C D 1 u m bers
11.4 Introduction To Advanced Instructions And Application
11.4.1:- 16- Bit Data Transfer (Copy) and Data Exchange Group
1 1 . 4 . 2 A r i t h m e t i c G r o u p
11.4.3 Instruction Related to the Stack Pointer and the Progra m Counter
1 1 . 4 . 4 M i s c e l l a n e o u s I n s t r u c t i o n
11.5 Multiplication
1 1 . 5 . 1 I l l u s t r a t i v e P r o g r a m : M u l t i p l i c a t i o n o f T w o 8 - B i t U n s i g ned 1umbers
11.6 Subtraction With Carry
1 1 . 6 . 1 I l l u s t r a t i v e P r o g r a m : 16-Bit Subtraction
11.7 Summary
4uestions and Programming Assignments



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11.0 Objectives
Write programs and subroutine to
x Convert a packed BCD number (0 -99) into its binary equivalent.
x Convert a binary digit ( 0 to F ) into its ASCII Hex code and vi ce versa.
x Select an appropriate seven-segment code for a given binary num ber using
the table look-up technique.
x Convert a binary digit ( 0 to F ) into its ASCII Hex code and vi ce versa.
x Decimal- adjust 8-bit BCD addition and subtraction.
x Perform such arithmetic operation as multiplication and subtrac tion using
16-bit data related instructions.
x Demonstrate uses of instructions such as DAD, PCHL,;THL, and ;C HG.
11.1 Introduction
In microprocessor applications, various number systems and cod es are used to
input data or to display results. The ASCII (American Standard Code for
Information Interchange) keyboard is a commonly used input devi ce for disk-
based microcomputer systems. Similarly, alphanumeric characters (letters and
numbers) are displayed on a CRT( cathode ray tube) terminal usi ng the ASCII code.
However, inside the microprocessor, data processing is usually performed in
binary. In some instances, arithmetic operations are performed in BCD numbers.
Therefore, data must be converted from one code to another code . The
programming techniques used for code conversion fall into four general categories.
1. Conversion based on position of adigit in a number (BCD to b inary and vice
versa) .
2. Conversion based on hardware consideration (binary to seven -segment code
using table look-up procedure).
3. Conversion based on sequential order of digits (binary to A SCII and vice
versa).
4. Decimal adjustment in BCD arithmetic operations. (This is an adjustment
rather than a code conversion).
This chapter discusses these techniques with various examples a s subroutines. The
subroutines are written to demonstrate industrial practices in writing software, and
can be verified on single- board microcomputers. In addition, i nstructions related
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11.2 BCD Addition
In some applications, input /output data are presented in decim al numbers, and the
speed of data processing is unim portant. In such applications, it may be convenient
to perform arithmetic operations directly in BCD numbers. Howev er, the addition
of two BCD numbers may not represent an appropriate BCD value. For example,
the addition of 34 BCD and 26 BCD results in 5AH as shown below: 34 10 0011 0100 BCD 26 10 0010 0110 BCD BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 6010 0101 1010 BCD The microprocessor cannot recognize BCD numbers it adds any tw o numbers in
binary.
In BCD addition, any number larger than 9 (from A to F) is inva lid and needs to be
adjusted by adding 6 in binary.
For example, after 9, the next BCD number is 10 However, in He x it is A. The
Hex number A can be adjusted as a BCD number by adding 6 in bin ary .The BCD
adjustment in 8-bit binary register can be shown as follows: A 0 0 0 0 1 0 1 0 6 0 0 0 0 0 1 1 0 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 0 0 0 1 0 0 0 0 10 BCD Any BCD sum can be adjusted to proper BCD value by adding 6 whe n the sum
exceeds 9 . In case of packed BCD, both BCD 1 and BCD 2 need to be adjusted if a
carry is generated b adding 6 to BCD 1, the carry should be added to BCD 2, as shown
in the following example.



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E[ample 11.1:- Add two packed BCD number: 77 and 48 . 77 0 1 1 1 0 1 1 1 48 0 1 0 0 1 0 0 0 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 125 1 0 1 1 1 1 1 1  0 1 1 0 BBBBBBBBBBBBBBBBBBBBBBBBBBBB C< 1 0 1 0 1  0 1 1 0 BBBBBBBBBBBBBBBBBBBBB C< 1 0 0 1 0 0 1 0 1
The value of the least signi ficant four bits is larger than 9. Add 6.
The value of the most significant four bits is larger than 9, A dd 6 and the carry from
the previous adjustment.
In this example, the carry is generated after the adjustment of the least significant
four bits for the BCD digit and is again added to the adjustmen t of the most
significant four bits.
A special instruction called DAA (decimal Adjust Accumulator ) performs the
function of adjusting a BCD sum in 8085 instruction set. This i nstruction uses the
Auxiliary Carry flip-flop (AC) to sense that the value of the l east four bits is larger
than 9 and adjusts the bits to the BCD value. Similarly, it use s the Carry flag (C<)
to adjust the most significant four bits. However, the AC flag is used internally by
the microprocessor this flag is not available to the programme r through any Jump
instruction.
Instruction
DAA : Decimal Adjust Accumulator
This is a 1- byte instruction
It adjusts an 8- bit number in the accumulator to form two BCD numbers by using
the process described above.
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211Chapter 11: BCD Arithmetic and 16-Bit Data Operation
All flags are affected.
It must be emphasized that instruction DAA
Adjust a BCD sum.
It does not convert a binary number into BCD numbers.
It works only with addition when BCD numbers are used  does no t work with
subtraction.
11.2 .1 Illustrative Program: Additi on of Unsigned BCD Numbers
Problem Statement
A set of ten packed BCD numbers is stored in the memory locatio n starting at
;;50H.
1. Write a program with a subroutine to add these numbers in B CD. If a carry
is generated, save it in register B, and adjust it for BCD. The final sum will
be less than 9999 BCD .
2. Write a second subroutine to unpack the BCD sum stored in re gisters A and
B, and store them in the output-buffer memory starting at ;;60H . The most
significant digit (BCD 4) should be stored at ;;60H and the least significant
digit (BCD 1) at ;;63H. START : L;I SP, STACK Initialize stack pointer L;I H, ;;50H  Point index to ;;50H MVI C,COU1T Load register C with the count of
BCD numbers to be added ;RA A  Clear accumulator MOV B,A  Clear register B to save carry 1;TBCD CALL BCDADD  Call subroutine to add BCD
numbers I1; H  Point to next memory location DCR C  One addition of BCD number is
complete, decrement the counter J1= / 1;TBCD If all numbers are added go to next
step, otherwise go back L;I H,;;63H Point index to store BCD 1 first munotes.in

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212MICROPROCESSOR ARCHITECTURE CALL U1PAK  Unpack the BCD stored in the
accumulator MOV A,B Get ready to store high-order
BCD- BCD 3 and BCD 4 CALL U1PAK  Unpack and store BCD 3 and
BCD 4 at ;;61H and ;;60H HLT BCDADD:  This subroutine adds the BCD number from the memory to
the accumulator and decimal adjusts it. If sum is larger than
eight bits, it saves the carry and decimal-adjusts the carry su m.
 Input : The memory address in HL register where the BCD
number is stored
Output : Decimal-adjusted BCD number in the accumulator
and the carry in register B ADD M  Add packed BCD byte and adjust it for
BCD sum. DAA R1C If no carry, go back to next BCD MOV D,A  If carry is generated, save the sum from
the accumulator MOV A,B  Transfer C< sum from register B and
add 01 ADI 01H DAA  Decimal-adjust BCD from B MOV B,A  Save adjusted BCD in B MOV A,D Place BCD 1 and BCD 2 in the
accumulator RET U1PAK:  This subroutine unpacks the BCD in the accumulator and the
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213Chapter 11: BCD Arithmetic and 16-Bit Data Operation Input : BCD number in the accumulator, and the buffer
address in HL registers
Output : Unpacked BCD in the output buffer MOV D,A  Save BCD number A1I 0FH Mask high-order BCD MOV M,A  Store low-order BCD DC; H  Point to next memory location MOV A,D  Get BCD again A1I F0H  Mask low-order BCD RRC RRC
RRC
RRC  Convert the most significant four bits
into unpacked BCD MOV M,A  Store high-order BCD DC; H  Point to the next memory location RET
Program Description
1. The expected maximum sum is 9090, which requires two regist ers. The main
program clears the accumulator to save BCD 1 and BCD 2, clears register B to
save BCD 3 and BCD 4, and call the subroutine to add the numbers. The BCD
bytes are added until the counter becomes zero.
2. The BCDADD subroutine is an illustration of the multiple en ding
subroutines. It adds a byte, decimal –adjusts the accumulator and, if there is
no carry, returns the program execution to the main program. If there is a
carry, it adds 01 to the carry register B by transferring the c ontents to the
accumulator and decimal-adjusting the contents. The final sum i s stored in
register A and B.
3. The main program calls the U1PAK subroutine,which takes the B C D
number from the accumulator (e.g. 57 BCD), unpacks it into two separate BCD
(e.g. 05 BCD and 07 BCD), stores them in the output buffer. When a subroutine
stores a BCD number in memory, it decrements the index because BCD 1 is
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214MICROPROCESSOR ARCHITECTURE
11.3 BCD Subtraction
When subtracting two BCD numbers, the instruction DAA cannot be used to
decimal adjust the result of two packed BCD numbers the instru ction applies only
to addition. Therefore, it is necessary to devise a procedure t o subtract two BCD
numbers. Two BCD num bers can be subtracted by using the procedure of 100’s
complement (also known as 10’s complement) , similar to 2’s complement. The
100’s complement of a subtrahend can be added to a minuend as illustrated :
For example, 82-48( 34) ca n be performed as follows:
100’s complement of subtrahend 52 (100 -48 52)
Add minuend 82
BBBBBBBBBBBB
1 / 34
The sum is 34 if the carry is ignore d. This is similar to subtraction by 2’s
complement .However in an 8-bit microprocessor it is not a sim ple process to find
100’s complement of a subtrahend (100 BCD requires twelve bits). Therefore, in
writing a program 100’s complement is obtained by finding 99’s complement and
adding 01.
11.3.1 Illustrative Problem: Subtraction of Two Packed BCD Numb ers
Problem Statement
Write a subroutine one packed BCD number from another BCD numbe r. The
minuend is placed in register B, and subtrahend is placed is re gister C by the calling
program. Return the answer into the accumulator.
Subroutine SUBBCD  This subroutine subtracts two BCD numbers and adjusts the resu lt
to BCD values by using the 100’s complement method.
 Input : A minuend in register B and a subtrahend in register C
 Output : The result is placed in the accumulator MVI A,99H SUB C ; Find 99’s complement of subtrahend I1R A ;Find 100’s complement of subtrahend ADD B ; Add minuend to 100’s complement of
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215Chapter 11: BCD Arithmetic and 16-Bit Data Operation
11.4 Introduction to Advanced Instructions and Application
The instructions deal primarily with 8-bit data (except L;I). H owever, in some
instances data larger than eight bits must be manipulated, espe cially in arithmetic
manipulations and stack operations. Even if the 8085 is an 8- b it microprocessor,
its architecture allows specific combinations of two 8-bit regi sters to form 16-bit
registers. Several instructions in the instruction set are avai lable to manipulate 16
bit data.
11.4.1:- 16- Bit Data Transfer (Cop y) and Data E[change Group LHLD:- Load HL registers direct
This is a 3-byte instruction.
The second and third bytes specify a memory location ( the seco nd
byte is a line number and the third byte is a page number) .
Transfers the contents of the specified memory location to L re gister.
Transfers the contents of the next memory location to H registe r SHLD:- Store HL registers direct This is a 3-byte instruction.
The second and third bytes specify a memory location ( the seco nd
byte is a line number and the third byte is a page number) .
Stores the contents of L register in the specified memory locat ion
Stores the contents of H register in the next memory location. ;CHG:- Exchange the contents of HL and DE
This is a 1-byte instruction
The contents of H register are exchanged with the contents of D
register, and the contents of L register are exchanged with the
contents of E register
E[ample 11.2:- Memory locations 2050H and 2051H contain 3FH and 42H,
respectively, and register pair DE contains 856FH. Write instru ctions to exchange
the contents of DE with the contents of the memory locations.
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216MICROPROCESSOR ARCHITECTURE
Instructions: Machine Code Mnemonics 2A 50
20 LHLD 2050 H 42 3F L 3F
42 2050
2051 EB ;CHG D 42 3F E
H 85 6F L 3F
42 2050
2051 22 50
20 SHLD 2050H
H 85 6F L 6F
85 2050
2051 11.4.2 Arithmetic Group Operation: : Addition with Carry ADC R ADC M
ACI 8-bit These instructions add the contents of
the operand, the carry, and the
accumulator. All flags are affected.
E[ample 11.3 Registers BC contain 2793H and register DE contain 3182H . Wri te
instructions to add these two16- bit numbers, and place the sum i n m e m o r y
locations 2050H and 2051H.
Before instructions: B 27 93 C D 31 82 E Instructions MOV A,C A 93 F 93 ADD E A 15 C< 1 F 82 MOV L,A H 15 L
1 /15H MOVA,B 27 ADC D 31 MOV H,A H 59 15 L
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217Chapter 11: BCD Arithmetic and 16-Bit Data Operation
Operation: Subtraction with Carry
SBB R
SBB M
SBI 8-bit
These instructions subtract the contents of the operand and bor row from the
contents of the accumulator.
E[ample 11.4 :- Register BC contains 8538H and registers DE contain 62A5H .
Write instructions to subtract the contents of DE from the cont ents of BC, and place
the result in BC.
Instructions MOV A,C (B) 85 38 (C) SUB E ------ MOV C,A (D) 62 A5 ( E ) MOV A,B BBBBBBBBBBBBBBBBBBBBBB -1 1 / 93 SBB D (B) 22 93 ( C) MOV B,A
Operation : Double Register ADD
DAD Rp
DAD B
DAD D
DAD H
DAD SP
Add register pair to HL
It is a 1-byt instruction
Adds the contents of the operand (register pair or stack pointe r) to the contents of
HL registers
The result is placed in HL registers
The Carry flag is altered to reflect the result of the 16-bit a ddition. 1o other flags
are affected.
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218MICROPROCESSOR ARCHITECTURE
E[ample 11.5 Write instructions of the stack pointer register at output por ts
Instructions L;I H, 0000H  Clear HL DAD SP  Place the stack pointer contents in HL MOV A,H  Place high-order address of the stack pointer in the
accumulator OUT PORT1 MOV A,L  Place low-order address of the stack pointer in the
accumulator OUT PORT2
The instruction DAD SP adds the contents of the stack pointer r egister to the HL
register pair, which is already cleared. This is only instructi on in the 8085 that
enables the programmer to exami ne the contents of the stack poi nter register.
11.4.3 Instruction Related to the Stack pointer and the Program Counter
;THL : Exchange Top of the Stack with H and L
The contents of L are exchanged with the contents of the memory location shown
by the stack pointer, and the contents of H are exchanged with the contents of
memory location of the stack pointer 1.
E[ample 11.6 :- Write a subroutine to set the =ero flag and check whether the
instruction J= (Jump on =ero) functions properly, without modif ying any register
contents other than flags.
Subroutine CHECK: PUSH H MVI L,FFH  Set all bits in L to logic 1 PUSH PSW Save flags on the top of the stack ;THL  Set all bits in the top stack
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219Chapter 11: BCD Arithmetic and 16-Bit Data Operation
The instruction PUSHPSW places the flags in the top location of the stack,and the
instruction ;THL changes all the bits in that location to logic 1 . The instruction
POPPSW sets all the flags.
If the instruction J= is functioning properly, the routine retu rns to the calling
program otherwise, it goes to the ERROR routine (not shown).
This example shows that the flags can be examined, and can be s et or reset to check
malfunctions in the instructions.
SPHL :- Copy H and L registers into the Stack Pointer Register
The contents of H specify the high-order byte and contents of L specify the low-
order byte.
The contents of HL registers are not affected.
This instruction can be used to l oad a new address in the stack pointer register.
PCHL :- Copy H and L registers into the Program Counter
The contents of H specify the high-order byte and the contents of L specify the low-
order byte.
11.4.4 Miscellaneous Instruction
CMC : Complement the Carry flag (C<)
If the Carry flag is 1, it is reset  if it is 0, it is set.
STC : Set the Carry Flag (C< 1)
11.5 Multiplication
Multiplication can be performed by repeated addition this tech nique is used in
BCD –to –binary conversion. It is however, an inefficient technique for a large
multiplier.
A more efficient technique can be devised by following the mode l of manual
multiplication of decimal numbers.



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220MICROPROCESSOR ARCHITECTURE
For example, 108 ; 15 BBBBBBBBBBB Step 1 : (108 ; 5) 540 Step 2 : shift left and add (108 ; 1) 108 1620 In this example, the multiplier multiplies each digit of the mu ltiplicand, starting
from the farthest right, and adds the product by shifting to th e left. The same process
can be applied in binary multiplication.
11.5.1 Illustrative Program: Multipl ication of Two 8-Bit Unsign ed Numbers
Problem Statement
A multiplicand is stored in memory location ;;50H and a multipl ier is stored in
location ;;51H. Write a main program to
1. Transfer the two numbers plac ed in registers H and L.
2. Store the product in the Output Buffer at ;;90H.
Write a subroutine to
1. Multiply two unsigned numbers placed in registers H and L.
2. Return the result into the HL pair.
Main Program L;I SP, STACK LHLD ;;50H  Place contents of ;;50 in L register and contents of
;;51 in H register ;CHG  Place multiplier in D and multiplicand in E CALL MLTPL<  Multiply the two numbers SHLD ;;90H  Store the product in locations ;;90 and 91H HLT
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Subroutine MLTPL< : This subroutine multiplies two 8-bit unsigned numbers  Input : Multiplicand in register E and mul tiplier in register D
 Output : Results in HL register MLTPL<: MOV A,D  Transfer multiplier to accumulator MVI D,00H  Clear D to use in DAD instruction L;I H,0000H  Clear HL MVI B,08H Set up register B to count eight rotations 1;TBIT: RAR Check if multiplier bit is 1 J1C 1OADD  If not, skip adding multiplicand DAD D  If multiplier is 1, add multiplicand to HL and
place partial result in HL. 1OADD: ;CHG  Place multiplicand in HL DAD H  And shift left ;CHG  Retrieve shifted multiplicand DCR B  One operation is complete, decrement counter J1= 1;TBIT  Go back to next bit RET
Program Description
1. The objective of the main program is to demonstrate use of the instruction
LHLD, SHLD, and ;CHG. The main program transfers the two bytes
(multiplier and multiplicand) from memory locations to the HL r egisters by
using the instruction LHLD, places them in DE register by the i nstruction
;CHG, and places the result in the Output Buffer by the instruc tion SHLD.
2. The multiplier routine follows the format –add and shift to the left. The
routine places the multiplier in the accumulator and rotates it eight times until
the counter (B) becomes zero. The reason for clearing D is to u se the
instruction DAD to add register pairs.
3. After each rotation, when a multiplier bit is 1, the instru ction DAD D
performs the addition,and DAD H, shifts bits to the left. When a bit is 0, the
subroutine skips the instruction DAD D and just shifts the bits .

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222MICROPROCESSOR ARCHITECTURE
11.6 Subraction with Carry
The instruction set includes several instructions specifying ar ithmetic operations
with carry. Description of these instructions convey an impress ion that these
instructions can be used to add ( or subtract ) 8- bit numbers hen the addition
generates carries.
In fact, in these instructions when a carry is generated, it is added to bit D 0 of the
accumulator in the next operation . Therefore, these instructio ns are used primarily
in 16- bit addition and subtra ction, as shown in the next progr am.
11.6.1 Illustrative Program: 16-Bit Subtraction
Problem Statement
A set of five 16-bit readings of the current consumption of in dustrial control units
is monitored by meters and stored at memory locations starting at ;;50H . The
low- order byte is stored first (e.g., at ;;50H), followed by t he high-order byte(e.g.
at ;;;51H) . The corresponding maximum limits for each control unit are stored
starting at ;;90H.
Subtract each reading from its specified limit, and store the d ifference in place of
the readings. If any reading exceeds the maximum limit, call th e indicator routine
and continue checking.
Main Program L;I D, 2050H  Point index to reading L;I H,2080H  Point index to maximum limits MVI B,05H  Set up B as a counter 1E;T: CALL SBTRAC Point to next location I1; D Point to next location I1; H DCR B J1= 1E;T HLT Subroutine
SBTRAC : This subroutine subtracts two 6- bit numbers
 Input : The contents of registers DE point t o reading locations
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223Chapter 11: BCD Arithmetic and 16-Bit Data Operation Output : The results are placed in reading locations, thus de stroying
the initial readings Memory Contents The first current
reading 6790H
2050H 90H 2051H 67H LSB MSB Maximum limit
7000H
2090H 00H 2091H 70H LSB MSB  Illustrative Example SBTRAC: MOV A,M (A) 00H LSB of maximum limit ;CHG  (HL) 2050H SUB M ; (A) = 0000 0000 2’s complement of 90H (M) 0111 0000 Borrow flag is set to
1 0111 0000 indicate the result is in
2’s complement. MOV M,A Store at 2050H ;CHG  (HL) 2090H I1; H  (HL) 2091H I1; D  (DE) 2051H MOV A,M  (A) 70H MSB of the maximum limit ;CHG  (HL) 2051H SBB M  (A) 0111 0000 ( 70H) ; (M) = 10011001 2’s complement of 67H
 (C<) 1 Borrow flag CC I1DIKET Call Indicate subroutine if reading is
higher than the maximum limit MOV M,A RET Program Description
This is a 16- bit subtraction routine that subtracts one byte a t a time. The low-order
bytes are subtracted by using the instruction SUB M . If a borr ow is generated, it is
accounted for by using the instruction SBB M (subtract with Car ry) for the high-
order bytes. In the illustrative example, the first subtraction (00H -90H) generates
a borrow that is subtracted from the high-order bytes. The inst ruction ;CHG
changes the index pointer alternately between the set of readin gs and the maximum
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11.7 Summary
16- bit Data transfer (copy) and data exchange instructions
LHLD, SHLD, ;CHG,;THL, PCHL,SPHL
Arithmetic Instructions used in 16- bit operations
The following instructions add the contents of the operand, the c a r r y , a n d t h e
accumulator.
ADC R, ADC M, ACI 8- bit
Subtraction: The following instructions subtract the contents o f the operand and the
borrow from the contents of the accumulator.
SBB R, SBB M, SBI 8-bit
4uestions and Programming Assignments
41) Explain BCD Addition with examples.
42) Write a counter program to count continuously from a 0 to 9 9 in BCD with a
delay of 750ms between each count. Display the count at an outp ut port.
43) Explain BCD Subtraction with examples.
44) Write a program to subtract a 2-digit BCD number from anot her 2-digit BCD
number .
45) Explain Multiplication with examples.
46) A set of 16- bit readings is stored n memory locations sta rting at 2050H .Each
reading occupies two memory locations: the low- order byte is s tored first,
followed by the high- order byte. The number of readings stored is specified
by the contents of B register. Write a program to add all the r eading and store
the sum in the Output-Buffer memory. ( The maximum limit of a sum is 24
bits).
Books and References
1. Computer System Architecture by M. Morris Mano, PHI Publication , 1998.
2. Structured Computer Organization by Andrew C. Tanenbaum, P HI
Publication.
3. Microprocessors Architecture, Programming and Application with 8085 by
Ramesh Gaonker,PE1RAM, Fifth Edition,2012.
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225Chapter 11: BCD Arithmetic and 16-Bit Data Operation
Books and References
1. Computer System Architecture by M. Morris Mano, PHI Public ation, 1998.
2. Structured Computer Organization by Andrew C. Tanenbaum, P HI
Publication.
3. Microprocessors Architecture, Programming and Application with 8085 by
Ramesh Gaonker, PE1RAM, Fifth Edition, 2012.

™™™


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UNIT 4
12
SOFTWARE DEVELOPMENT
SYSTEM AND ASSEMBLERS
Unit Structure
12.1 Objectives
12.2 Introduction
12.3 Microprocessors-Based Software Development system
12.4 Operating System and Programming Tools
12.5 Assemblers and Cross-Assemblers, Writing Program Using Cr oss
Assemblers.
12.1 Objectives
At the end of this chapter, the student will be able to
x Illustrate the concept of Microproc essor-Based Software Develop ment System
x Describe the concept of oper ating system and programming tools
x Explain the assemblers and Cross-Assemblers
x Write the program using cross Assemblers
12.2 Introduction
1. The assembly language level differs in a significant respe ct from the micro-
architecture, ISA and operating system machine levels- it is im plemented by
translation rather than by interpretation.
2. Programs that convert a user’s program written in some language to another
language are called translators.
3. The language in which the original program is written is ca lled the source
language and the language to which it is converted is called th e target
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227Chapter 12: Software Development System and Assemblers4. Translation is used when a processor (either hardware or an interpreter) is
available for the target language but not for the source langua ge. If the
translation has been performed correctly, running the translate d program will
give precisely the same results as the execution of the source program would
have given had a processor for it been available.
5. In translation, the original program in the source language i s n o t d i r e c t l y
executed. Instead it is converted to an equivalent program cal led an object
program or executable binary program whose execution is carried out only
after the translation has been completed.
6. While the object program is being executed, only three leve ls are in evidence,
the micro-architecture level, the ISA level and the operating s ystem machine
level and these programs are found on computer’s memory during their
execution, this is possible due to advancement in microprocesso r in software
level with respect to operating system and assemblers.
7. So in this chapter we will going to study more about operat ing system and its
programming tools along with assemblers , cross assemblers.
12.3 Microprocessors-Based Software Development System
1. It is simply a computer that enables the user to write, mod ify, debug and test
programs.
2. In a microprocessor-based development system, a microproces sor is used to
develop software for a particular microprocessor.
3. Generally, the microprocessor has a large R/W memory(typica lly 8M to 64
M), disk storage, and a video terminal with an ASCII keyboard.
4. The System(I/Os, files, programs etc) is managed by a prog ram called the
operating system.
5. Software development system i ncludes an ASCII keyboard, a C RT terminal,
an MPU board with 8M to 64M R/W memory and disc controllers and disk
drivers.
6. The disk controller is an interfacing circuit through which the microprocessor
unit can access a disk and provide Read/Write control signals.
7. The disk drives have Read/Write elements, which are respons ible for reading
and writing data on the disk.
8. At present, most systems are equipped a 3.5-inch disk stores 1.44M bytes of
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228MICROPROCESSOR ARCHITECTURE9. The Storage capacity of a typical hard disk in a PC is 2.2G (giga) bytes or
higher.
10. Floppy disk- It is made up of a thin magnetic material(iro n oxide) that can
store logic 0s and 1s in the form of magnetic direction. The su rface on the
disk is divided in to a number of concentric tracks, and each t rack is divided
in to sectors.Data are stored on concentric circular tracks on both
sides(known as doubled- sided). At the edge of the disk there is a ‘notch’
called write protected notch.

Fig. 1 - Image of Floppy Disk
11. Hard Disk- Another type of storage memory used with computers c alled a
hard disk. In general the disk is fastened in a dust free drive mechanism. It is
highly precise and reliable. It requires sophisticated controll er circuitry. It is
more stable than the floppy disk. They are available in various sizes and their
storage capacity is quite large in the order of gigabytes.

Fig. 2 - Image of Hard Disk
12. CD-ROM- A CD-ROM is a optical disk that uses a laser beam to st ore digital
information that can be read with a laser diode. The disk is im mune to dust
and mechanical wear because of its optical nature.It comes in v arious
size(3.5-14 inch) and stores huge amount of data from 100 mb to several gb.
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Fig. 3 - Image of CD-ROM
12.4 Operating System and Programming Tools
1. The operating system of a computer is a group of programs t hat manages or
oversees all the operations of the computer.
2. The Computer transfers information constantly among peripher als such as a
floppy disk, printer, keyboard and video monitor.
3. It also stores user programs under file name on a disk. Eac h computer has its
own operating system like MS-DOS(microsoft Disk Operating Syste m),
OS/2(Operating system 2), Windows 95, Windows xp, Windows 7,10 etc and
Unix.
4. Older version of operating system like MS-DOS is being repl aced by newer
version such as microsoft windows newer versions, IBM OS/2 and unix/linux.
5. MS-DOS(Microsoft Disk Operating System)- It is a single user o p e r a t i n g
system used normaly in PC’s.
5.1 History of DOS- a) In 1979, a small company called seattl e computer
products wrote its own OS names as ODOS. IBM purchased ODOS
and then took the help of microsoft to develop a new product. T his
product was announced with IBM-PC in 1981 with names as MS-
DOS version 1.0. b)In 1983 MS-DOS ver 2.0 appeared with many
advances in design. It was made for PC announced by IBM. It
introduced fixed disk formatting, back up utilities and filter
commands for redirection of input/output operations.
5.2 Features- a) MS-DOS has enhanced version MS-DOS 7.0 in mar ket
which has GUI(Graphical user interface) facility. b)In 1991 tie up
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230MICROPROCESSOR ARCHITECTUREbetween IBM and Microsoft ended and microsoft started new serie s
which name is window operating system.c)1981- DOS1.1 Renamed
version of 4DOS(4uick and Dirty operating system) which was
purchased by Microsoft from Seattle Computer products. d)1982-
supported use of double sided disks. e)1983-DOS 2.0 supported
IBM’s 10 mb hard disk and some other additional features. f)1984-
DOS 3.0 support for high density 3.5 inch floppy disk. Allowed
partition on hard disk. g)1991- DOS 5.0, much upgraded version
included text editor and improved BASIC interpreter etc. h) 199 3-
DOS 6.0- Added a disk compression utility antivirus program and disk
defragmenter. i)1995- DOS 7.0, this version is part of MS windo ws
95, supports long file names but remove a large number of utili ties.
j)1997-DOS 7.1, support for FAT 32 hard disks and is part of la ter
versions of MS windows 95.
5.3 MS-DOS parts- The DOS OS is a set of programs which are s tored on
some secondary storage device, normally on floppy disk. It is t hen
loaded in to RAM when required. The DOS software is divided in to
three parts stored in three different files on disk. The disk w hich
contains these three files is called a Bootable disk.
5.4 The three files loaded on this disk are IO.SCOMMA1D.COM. The IO.Sthe standard devices such as keyboard, disk, floppy, printer an d
monitor are present. All these device drivers are often called
BIOS(Basic Input Output System). The MSDOS.Scalled DOS Kernel. It contains all the modules for process
management. These modules are written in machine independent
manner so that they could be easily ported.
5.5 File in DOS-A file is a organized collection of data stor ed on storage
device such as magnetic tape, disk. The file is used to store o nly one
kind of information. Different types of files are used in compu ter such
as text file, batch file, database file etc. Some file extensio ns and their
meanings
9 .CC Source program file
9 .ftn Fortran source program file
9 .pas Pascal Source program file
9 .obj object file
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